Datasheet

Read and Write Command Interval
Table 43. Minimum Read and Write Command Timings
Bank Group
Access type
Timing Parameter
Note
Same
Minimum Read to Write
CL - CWL + RBL / 2 + 1 t
CK
+ t
WPRE
1,2
Minimum Read after Write
CWL + WBL / 2 + t
WTR_L
1,3
Different
Minimum Read to Write
CL - CWL + RBL / 2 + 1 t
CK
+ t
WPRE
1,2
Minimum Read after Write
CWL + WBL / 2 + t
WTR_S
1,3
Note 1. These timings require extended calibrations times t
ZQinit
and t
ZQCS
.
Note 2. RBL: Read burst length associated with Read command
RBL = 8 for fixed 8 and on-the-fly mode 8
RBL = 4 for fixed BC4 and on-the-fly mode BC4
Note 3. WBL: Write burst length associated with Write command
WBL = 8 for fixed 8 and on-the-fly mode 8 or BC4
WBL = 4 for fixed BC4 only
Write Timing Violations
The following write timing diagram is to help understanding of each write parameter's meaning and just examples.
The details of the definition of each parameter will be defined separately.
Motivation
Generally, if Write timing parameters are violated, a complete reset/initialization procedure has to be initiated
to make sure that the DRAM works properly. However, it is desirable, for certain violations as specified below,
the DRAM is guaranteed to not “hang up” and that errors are limited to that particular operation.
For the following, it will be assumed that there are no timing violations with regards to the Write command itself
(including ODT, etc.) and that it does satisfy all timing requirements not mentioned below.
Data Setup and Hold Offset Violations
Should the data to strobe timing requirements (t
DQS_off
, t
DQH_off
, t
DQS_dd_off
, t
DQH_dd_off
) be violated, for any of the
strobe edges associated with a write burst, then wrong data might be written to the memory locations
addressed with this write command.
In the example (Write Burst Operation WL = 9 (AL = 0, CWL = 9, BL8), the relevant strobe edges for write
burst A are associated with the clock edges: T9, T9.5, T10, T10.5, T11, T11.5, T12, T12.5.
Subsequent reads from that location might results in unpredictable read data, however the DRAM will work
properly otherwise.
Strobe and Strobe to Clock Timing Violations
Should the strobe timing requirements (t
DQSH
, t
DQSL
, t
WPRE
, t
WPST
) or the strobe to clock timing requirements
(t
DSS
, t
DSH
, t
DQSS
) be violated for any of the strobe edges associated with a Write burst, then wrong data might
be written to the memory location addressed with the offending Write command. Subsequent reads from that
location might result in unpredictable read data, however the DRAM will work properly otherwise with the
following constraints:
1) Both Write CRC and data burst OTF are disabled; timing specifications other than t
DQSH
, t
DQSL
, t
WPRE
, t
WPST
,
t
DSS
, t
DSH
, t
DQSS
are not violated.
2) The offending write strobe (and preamble) arrive no earlier or later than six DQS transition edges from the
Write-Latency position.
3) A Read command following an offending Write command from any open bank is allowed.
4) One or more subsequent WR or a subsequent WRA {to same bank as offending WR} may be issued t
CCD_L
later but incorrect data could be written; subsequent WR and WRA can be either offending or non-offending
writes. Reads from these Writes may provide incorrect data.
5) One or more subsequent WR or a subsequent WRA {to a different bank group} may be issued t
CCD_S
later
but incorrect data could be written; subsequent WR and WRA can be either offending or non-offending
writes. Reads from these Writes may provide incorrect data.
6) Once one or more precharge commands(PRE or PREA) are issued to DDR4 after offending write command
and all banks become precharged state(idle state), a subsequent, non-offending WR or WRA to any open
bank shall be able to write correct data.
AS4C256M16D4
Confidential
- 128 of 201 -
Rev.1.0 Aug.2019