Datasheet
DON'T CARE
NOTE 1. BL = 8, AL = 0, CWL = 9, Preamble = 1t
CK
, t
CCD_S/L
= 6
NOTE 2. Din n (or b) = data-in to column n (or column b).
NOTE 3. DES commands are shown for ease of illustration; other commands may be valid at these times.
NOTE 4. BL8 setting activated by either MR0[A1A:0 = 0:0] or MR0[A1A:0 = 0:1] and A12 =1 during WRITE command at T0 and T6.
NOTE 5. BC4 setting activated by MR0[A1:A0 = 0:1] and A12 =0 during WRITE command at T0 and T6.
NOTE 6. CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable, Write CRC = Enable.
NOTE 7. The write recovery time (t
WR
) and write timing parameter (t
WTR
) are referenced from the first rising clock edge after the last write data shown at T19.
T0 T1 T6 T7 T8 T9 T10 T11
T12
T13
TRANSITIONING DATA
CK#
CK
DQ
CMD
T15
DESWRITE WRITE DES READ DES DES DES DES DES DES
DES
ADDR
DES
T16 T17
DES
DES
T18 T19
DES
T20
DQ
WL = AL + CWL = 9
Bank
Col b
Bank
Col n
BG a or
BG b
BG a
Bank Group
ADDR
DQS, DQS#
t
WR
4 Clocks
t
WTR
BL = 8
BC = 4 (OTF)
Din
n
Din
n+1
Din
n+2
Din
n+7
Din
n+3
Din
n+4
Din
n+5
Din
n+6
Din
b
Din
b+1
Din
b+2
CRC
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
Din
n
Din
n+1
Din
n+2
Din
n+3
Din
b
Din
b+1
Din
b+2
Din
b+3
t
RPRE
t
WPST
t
CCD_S/L = 6
CRC
WL = AL + CWL = 9
CRC CRC
Figure 151. Nonconsecutive WRITE (BL8/BC4) OTF with 1t
CK
Preamble and Write CRC in Same or
Different Bank Group
DON'T CARE
NOTE 1. BL = 8, AL = 0, CWL = 9 + 1 = 109, Preamble = 2t
CK
, t
CCD_S/L
= 7
NOTE 2. Din n (or b) = data-in to column n(or column b).
NOTE 3. DES commands are shown for ease of illustration; other commands may be valid at these times.
NOTE 4. BL8 setting activated by either MR0[A1:A0 = 0:0] or MR0[A1:A0 = 0:1] and A12 =1 during WRITE command at T0 and T7.
NOTE 5. BC4 setting activated by MR0[A1:A0 = 0:1] and A12 =0 during WRITE command at T0 and T7.
NOTE 6. CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable, Write CRC = Enable.
NOTE 7. t
CCD_S/L
= 6 isn’t allowed in 2t
CK
preamble mode.
NOTE 8. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T21.
NOTE 9. When operating in 2t
CK
Write Preamble Mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL
Setting supported in the applicable t
CK
range. That means CWL = 9 is not allowed when operating in 2t
CK
Write Preamble Mode.
T0 T1 T7 T8 T9 T10 T11 T12
T13
T14
TRANSITIONING DATA
CK#
CK
DQ
CMD
T15
DESWRITE WRITE DES READ DES DES DES DES DES DES
DES
ADDR
DES
T16 T17
DES
DES
T18 T19
DES
T20
DQ
WL = AL + CWL = 10
Bank
Col b
Bank
Col n
BG a or
BG b
BG a
Bank Group
ADDR
DQS, DQS#
t
WR
4 Clocks
t
WTR
BL = 8
BC = 4 (OTF)
Din
n
Din
n+1
Din
n+2
Din
n+7
Din
n+3
Din
n+4
Din
n+5
Din
n+6
Din
b
Din
b+1
Din
b+2
CRC
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
Din
n
Din
n+1
Din
n+2
Din
n+3
Din
b
Din
b+1
Din
b+2
Din
b+3
t
WPRE
t
WPST
t
CCD_S/L = 7
CRC
T21 T22
DES DES
WL = AL + CWL = 10
CRC CRC
Figure 152. Nonconsecutive WRITE (BL8/BC4) OTF with 2t
CK
Preamble and Write CRC in Same or
Different Bank Group
AS4C256M16D4
Confidential
- 126 of 201 -
Rev.1.0 Aug.2019