Datasheet
DESWRITE DES DES DES DES DES DES DES DES DES
NOTE 1.BL8, WL=9 (AL=0, CWL=9)
NOTE 2. Din n = data-in to column n.
NOTE 3. DES commands are shown for ease of illustration : other commands may be valid at these times.
NOTE 4. BL8 stting activated by either MR0[A1:0=00] or MR0[A1:0=01] and A12=1 during WRITE command at T0.
NOTE 5. t
DQSS
must be met at each rising clock edge.
T0 T1 T2 T8 T9 T10 T11 T12 T13 T14
T15
CK#
CK
WL = AL + CWL
DON'T CARETRANSITIONING DATA
BG,Bank
Col n
t
DQSS(min)
t
WPRE
t
DQSH(min)
t
DQSL
t
DQSS
t
DSH
t
DQSH
t
DQSL
t
DQSH
t
DQSL
t
DQSH
t
DQSL
t
DQSH
t
DQSL(min)
t
DSH
t
DSH
t
WPST
t
DSS
t
DSS
t
DSS
t
DSS
t
DSS
t
DQSS(nominal)
t
WPRE
t
DQSH(min)
t
DQSL
t
DSH
t
DQSH
t
DQSL
t
DQSH
t
DQSL
t
DQSH
t
DQSL
t
DQSH
t
DQSL(min)
t
DSH
t
DSH
t
DSH
t
WPST
t
DSS
t
DSS
t
DSS
t
DSS
t
DSS
t
DSH
DQ
2
Din
n
Din
n+2
Din
n+3
DM#
t
DQSS(max)
t
WPRE
t
DQSH(min)
t
DQSL
t
DSH
t
DQSH
t
DQSL
t
DQSH
t
DQSL
t
DQSH
t
DQSL
t
DQSH
t
DQSL(min)
t
DSH
t
DSH
t
DSH
t
WPST
t
DSS
t
DSS
t
DSS
t
DSS
t
DSS
Din
n+4
Din
n+6
Din
n+7
t
DQSS
CMD
3
ADD
4
DQS, DQS#
DQS, DQS#
DQS, DQS#
Figure 124. Write Timing Definition and Parameters with 2t
CK
Preamble
Write Data Mask
One write data mask (DM#) pin for each 8 data bits (DQ) will be supported on DDR4 SDRAMs, consistent with
the implementation on DDR3 SDRAMs. It has identical timings on write operations as the data bits as shown
above, and though used in a unidirectional manner, is internally loaded identically to data bits to ensure
matched system timing. DM# is not used during read cycles, however, x16 organization as DBI# during write
cycles if enabled by the MR5[A11] setting. For more detail see section "Data Mask (DM), Data Bus Inversion
(DBI)".
Table 41. Reference Voltage for t
WPRE
Timing Measurements
Symbol
Parameter
Vsw1
Vsw2
Unit
t
WPRE
DQS, DQS# differential Write Preamble
V
IHDiff_DQS
x 0.1
V
IHDiff_DQS
x 0.9
V
The method for calculating differential pulse widths for t
WPRE2
is same as t
WPRE
.
Table 42. Reference Voltage for t
WPST
Timing Measurements
Symbol
Parameter
Vsw1
Vsw2
Unit
t
WPST
DQS, DQS# differential Write Postamble
V
IHDiff_DQS
x 0.9
V
IHDiff_DQS
x 0.1
V
AS4C256M16D4
Confidential
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Rev.1.0 Aug.2019