Datasheet

V
DD
Slew rate at Power-up Initialization Sequence
Table 4. V
DD
Slew Rate
Symbol
Min.
Max.
Units
Notes
V
DD
_sl
0.004
600
V/ms
1,2
V
DD
_ona
-
200
ms
3
Notes:
1. Measurement made between 300mv and 80% V
DD
minimum.
2. 20 MHz bandlimited measurement.
3. Maximum time to ramp V
DD
from 300 mv to V
DD
minimum.
Reset Initialization with Stable Power
The following sequence is required for Reset at no power interruption initialization:
1. Asserted Reset# below 0.2 x V
DD
anytime when reset is needed (all other inputs may be undefined). Reset#
needs to be maintained for minimum t
PW_Reset
. CKE is pulled "low" before Reset# being de-asserted (min.
time 10 ns).
2. Follow steps 2 to 10 in “Power-up Initialization Sequence”.
3. The Reset sequence is now completed, DDR4 SDRAM is ready for Read/Write training (include V
REF
training and Write leveling)
CK#
Tb Tc Td Te Tf Tg Th Ti TjTa
RESET#
CK
t
CKSRX
Tk
t
PW_Reset
500μs
t
XPR
t
MRD
t
MRD
t
MRD
t
MOD
t
ZQinit
MRSNote 1 MRS MRS MRS ZQCL Note 1 VALID
MRxMRx MRx MRx VALID
VALID
Static LOW in case R
TT_NOM
is enabled at time Tg, otherwise static HIGH or LOW
VDD,VDDQ
CMD
CKE
BA
ODT
RTT
10ns
t
IS
t
IS
t
IS
t
IS
NOTE 1. From time point "Td" until "Tk " DES commands must be applied between MRS and ZQCL commands.
NOTE 2. MRS Commands must be issued to all Mode Registers that have defined settings.
VPP
VALID
DON'T CARETIME BREAK
t
DLLK
Figure 5. Reset Procedure at Power Stable
AS4C256M16D4
Confidential
- 10 of 201 -
Rev.1.0 Aug.2019