Datasheet

Cycle to cycle period jitter t
JIT
(cc)
-
140
p
s
Cycle to cycle period j
itter during DLL
locking period
t
JIT
(cc,lck)
-
120
ps
Cumulative error across 2 cycles t
ERR
(2per)
-103
103
ps
Cumulative
error across 3 cycles t
ERR
(3per)
-122
122
ps
Cumulative error across 4 cycles t
ERR
(4per)
-136
136
ps
Cumulative error across 5 cycles t
ERR
(5per)
-147
147
ps
Cumulative
error across 6 cycles t
ERR
(6per)
-155
155
ps
Cumulative
error across 7 cycles t
ERR
(7per)
-163
163
ps
Cumulative
error across 8 cycles t
ERR
(8per)
-169
169
ps
Cumulative error across 9 cycles t
ERR
(9per)
-175
175
ps
Cumulative error across 10 cycles t
ERR
(10per)
-180
180
ps
Cumulative error across 11 cycles t
ERR
(11per)
-184
184
ps
Cumulative error across 12 cycles t
ERR
(12per)
-188
188
ps
Cumulative error across
n = 13,14,...49,50 cycles
t
ERR
(nper)
t
ERR
(nper)min = (1 + 0.68ln(n))*t
JIT
(per)min
t
ERR
(nper)max = (1 + 0.68ln(n))*t
JIT
(per)max
ps
32
Parameter Symbol
- 12 (DDR3L-1600)
Unit Note
Min
Max
AS4C256M16D3LB-12BIN
AS4C256M16D3LB-12BCN
Confidential
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Rev.1.1 Jan. 2017