Datasheet
Mode Register MR0
The Mode Register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It con-
trols burst length, read burst type, CAS
latency, test mode, DLL reset, WR and DLL control for precharge
power-down, which include various vendor specific options to make DDR3 SDRAM useful for various appli-
cations. The mode register is written by asserting low on CS
, RAS, CAS, WE, BA0, BA1 and BA2, while
controlling the states of address pins according to the table below.
Address Field
A7
mode
0Normal
1Test
A3 Read Burst Type
0 Nibble Sequential
1Interleave
A8
DLL Reset
0No
1Yes
Mode Register 0
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
TM CAS Latency RBTDLL
0*
1
WR
Write recovery for autoprecharge
A11 A10 A9 WR(cycles)
000 Reserved
001
5
*2
010
6
*2
011
7
*2
100
8
*2
101
10
*2
110
12
*2
111 Reserved
A
14-
0
BL
A1 A0 BL
0 0 8 (Fixed)
0 1 4 or 8(on the fly)
1 0 4 (Fixed)
1 1 Reserved
*1 : BA2, A13 and A14 are reserved for future use and must be programmed to 0 during MRS.
*2 : WR(write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the
next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR value in the mode register must be programmed to be equal or
larger than WRmin. The programmed WR value is used with tRP to determine tDAL.
BA
2
0*
1
BA1 BA0 MRS mode
00 MR0
01 MR1
10 MR2
11 MR3
A
12
PPD
A12
DLL Control for
Precharge PD
0 Slow exit (DLL off)
1 Fast exit (DLL on)
CAS Latency
A6 A5 A4 A2 Latency
0000 Reserved
0010 5
0100 6
0110 7
1000 8
1010 9
1100 10
1110
11
CL
A
13
AS4C256M16D3B-12BIN
AS4C256M16D3B-12BCN
Confidential
- 9/41 -
Rev.1.1 April 2017