Datasheet

Reset and Initialization with Stable Power
The following sequence is required for /RESET at no power interruption initialization.
1. Assert /RESET below 0.2 x VDD anytime when reset is needed (all other inputs may be undefined). /RESET needs to
be maintained for minimum 100ns. CKE is pulled low before /RESET being de-asserted (minimum time 10ns).
2. Follow Power-Up Initialization Sequence steps 2 to 11.
3. The reset sequence is now completed; DDR3 SDRAM is ready for normal operation.
1) From time point ‘Td’ until ‘Tk’, NOP or DES commands must be applied between MRS and ZQCL commands
V
DD
/V
DDQ
CK,CK
RESET
Tc . T d . Te . Tf . . Th . Ti . Tj . T kTg
t
CKSRX
Ta . Tb
CKE
200 us 500 us
10 ns
t
IS
*) MRS
MR2
MRS
MR3
MRS
MR1
MRS
MR0
ZQCL
t
XPR
**
t
IS
t
MRD
t
MRD
t
MRD
t
MOD
CMD
BA[2:0]
t
IS
ODT
DRAM_RTT
t
DLLK
Static LOW in case RTT_Nom is eanbled at time Tg, otherwise static HIGH or LOW
t
ZQinit
1) VALID
VALID
VALID
t
IS
V
DD
/V
DDQ
CK,CK
RESET
Tc.Td.Te.Tf. .Th.Ti.Tj.Tk.TgTa . Tb
CKE
100 ns 500 us
10 ns
t
IS
1) MRS
MR2
MRS
MR3
MRS
MR1
MRS
MR0
ZQCL
t
XPR
t
IS
t
MRD
t
MRD
t
MRD
CMD
BA[2:0]
t
IS
ODT
DRAM_RTT
1) From time point ‘Td’ until ‘Tk’, NOP or DES commands must be applied between MRS and ZQCL commands
t
CKSRX
t
MOD
t
ZQin
t
DLLK
Static LOW in case RTT_Nom is eanbled at time Tg, otherwise static HIGH or LOW
1) VALID
VALID
VALID
AS4C256M16D3B-12BIN
AS4C256M16D3B-12BCN
Confidential
- 8/41 -
Rev.1.1 April 2017