Datasheet

AC Characteristics
( VDD = 1.5V±0.075V; VDDQ =1.5V±0.075V )
Parameter Symbol
- 12 (DDR3-1600)
Unit NoteMin Max
Average clock cycle time t
CK
(avg)
Please refer Speed Bins
ps
Minimum clock cycle time
(DLL-off mode)
t
CK
(DLL-off)
8 - ns
6
Average CK high level width t
CH
(avg) 0.47 0.53 t
CK
(avg)
Average CK low level width t
CL
(avg) 0.47 0.53 t
CK
(avg)
Active Bank A to Active Bank B
command period
t
RRD
7.5 - ns
4 - nCK
Four activate window t
FAW
40 - ns
Address and Control input hold time
(VIH/VIL (DC100) levels)
t
IH
(base)
DC100
120 - ps
16
Address and Control input setup time
(VIH/VIL (AC175) levels)
t
IS
(base)
AC175
45 - ps
16
Address and Control input setup time
(VIH/VIL (AC150) levels)
t
IS
(base)
AC150
170 - ps
16,24
DQ and DM input hold time
(VIH/VIL (DC100) levels)
t
DH
(base)
DC100
45 - ps
17
DQ and DM input setup time
(VIH/VIL (AC175) levels)
t
DS
(base)
AC175
- - ps
17
DQ and DM input setup time
(VIH/VIL (AC150) levels)
t
DS
(base)
AC150
10 - ps
17
Control and Address Input pulse width
for each input
t
IPW
560 - ps
25
DQ and DM Input pulse width
for each input
t
DIPW
360 - ps
25
DQ high impedance time t
HZ
(DQ) - 225 ps
13,14
DQ low impedance time t
LZ
(DQ) -450 225 ps
13,14
DQS, DQS high impedance time
(RL + BL/2 reference)
t
HZ
(DQS) - 225 ps
13,14
DQS, DQS low impedance time
(RL - 1 reference)
t
LZ
(DQS) -450 225 ps
13,14
DQS, DQS to DQ Skew,
per group, per access
t
DQSQ
- 100 ps
12,13
CAS to CAS command delay t
CCD
4 - nCK
DQ output hold time from DQS, DQS
t
QH
0.38 - t
CK
(avg)
12,13
DQS, DQS rising edge output
access time from rising CK, CK
t
DQSCK
-225 225 ps
12,13
DQS latching rising transitions
to associated clock edges
t
DQSS
-0.27 0.27 t
CK
(avg)
DQS falling edge hold time
from rising CK
t
DSH
0.18 - t
CK
(avg)
29
DQS falling edge setup time
to rising CK
t
DSS
0.18 - t
CK
(avg)
29
Confidential
- 34/41 -
Rev.1.1 April 2017
AS4C256M16D3B-12BIN
AS4C256M16D3B-12BCN