Datasheet

DDR3-1600 Speed Bins
Speed Bin
- 12 (DDR3-1600)
Unit Notes
CL-nRCD-nRP 11-11-11
Parameter Symbol Min Max
Internal read command to first data tAA 13.75
(13.125)
20 ns
9
Active to read or write delay time tRCD 13.75
(13.125)
-ns
9
Precharge command period tRP 13.75
(13.125)
-ns
9
Active to active/auto-refresh command time tRC 48.75
(48.125)
-ns
9
Active to precharge command period tRAS 35 9 * tREFI ns
8
Average Clock
Cycle Time
CL = 5 CWL = 5 tCK(avg) 3.0 3.3 ns 1,2,3,7
CWL = 6,7 tCK(avg) Reserved Reserved ns 4
CL = 6 CWL = 5 tCK(avg) 2.5 3.3 ns 1,2,3,7
CWL = 6 tCK(avg) Reserved Reserved ns 4
CWL = 7 tCK(avg) Reserved Reserved ns 4
CL = 7 CWL = 5 tCK(avg) Reserved Reserved ns 4
CWL = 6 tCK(avg) 1.875 < 2.5 ns 1,2,3,7
CWL = 7 tCK(avg) Reserved Reserved ns 4
CL = 8 CWL = 5 tCK(avg) Reserved Reserved ns 4
CWL = 6 tCK(avg) 1.875 < 2.5 ns 1,2,3,7
CWL = 7 tCK(avg) Reserved Reserved ns 4
CL = 9 CWL = 5, 6 tCK(avg) Reserved Reserved ns 4
CWL = 7 tCK(avg) 1.5 < 1.875 ns 1,2,3,7
CL = 10 CWL = 5, 6 tCK(avg) Reserved Reserved ns 4
CWL = 7 tCK(avg) 1.5 < 1.875 ns 1,2,3,7
CWL = 8 tCK(avg) Reserved Reserved ns 4
CL = 11 CWL = 5, 6,7 tCK(avg) Reserved Reserved ns 4
CWL = 8 tCK(avg) 1.25 < 1.5 ns 1,2,3
Supported CL setting
5, 6, 7, 8, 9,10
nCK
Supported CWL setting 5, 6, 7, 8 nCK
Confidential
- 32/41 -
Rev.1.1 April 2017
AS4C256M16D3B-12BIN
AS4C256M16D3B-12BCN