Datasheet

Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS

Single-ended requirements for differential signals

Each individual component of a differential signal (CK, DQS, CK

, DQS) has also to comply with certain

requirements for single-ended signals.

CK and CK

have to approximately reach VSEH min / VSEL max [ approximately equal to the AC-levels

( VIH(AC) / VIL(AC) ) for Address/command signals ] in every half-cycle.

DQS, DQS

have to reach VSEH min / VSEL max [ approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ

signals ] in every half-cycle proceeding and following a valid transition.

Note that the applicable AC-levels for Address/command and DQ’s might be different per speed-bin etc.

E.g. if VIH150(AC) / VIL150(AC) is used for Address/command signals, then these AC-levels apply also for

the single-ended components of differential CK and CK

Slew Rate [V/ns]

tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV

Min. Max. Min. Max.

> 4.0 75 - 175 -

4.0 57 - 170 -

3.0 50 - 167 -

2.0 38 - 163 -

1.8 34 - 162 -

1.6 29 - 161 -

1.4 22 - 159 -

1.2 13 - 155 -

1.0 0 - 150 -

< 1.0 0 - 150 -

AS4C256M16D3B-12BIN

AS4C256M16D3B-12BCN

Confidential

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Rev.1.1 April 2017