Datasheet
Mode Register MR3
The Mode Register MR3 controls Multi Purpose Registers (MPR). The Mode Register 3 is written by assert-
ing low on CS
, RAS, CAS, WE, high on BA1 and BA0, and low on BA2 while controlling the states of
address pins according to the table below.
Burst Length (MR0)
Read and write accesses to the DDR3 are burst oriented, with the burst length being programmable, as
shown in the figure MR0 Programming. The burst length determines the maximum number of column loca-
tions that can be accessed for a given read or write command. Burst length options include fixed BC4, fixed
BL8, and on the fly which allows BC4 or BL8 to be selected coincident with the registration of a read on write
command Via A12 (BC
). Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
Burst Chop
In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles
earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two
clocks. In case of burst length being selected on the fly via A12(BC
), the internal write operation starts at the
same point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting
point for tWR and tWTR will not be pulled in by two clocks.
Mode Register 3
Address Field
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
A
14 -
1
0*
1
BA
2
0*
1
A
12
MPR Address
A1 A0
MPR location
00
Predefined pattern*
2
01
10
11
MPR Operation
A2
MPR
0
Normal operation*
3
1 Dataflow from MPR
MPR Loc
MPR
* 1 : BA2, A3 - A14 are reserved for future use (RFU) and must be programmed to 0 during MRS.
* 2 : The predefined pattern will be used for read synchronization.
* 3 : When MPR control is set for normal operation, MR3 A[2] = 0, MR3 A[1:0] will be ignored
BA1 BA0 MRS mode
00 MR0
01 MR1
10 MR2
11 MR3
RFU
RFU
RFU
A
13
AS4C256M16D3B-12BIN
AS4C256M16D3B-12BCN
Confidential
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Rev.1.1 April 2017