Datasheet
Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom
impedance, additive latency, write leveling enable and Qoff.
The Mode Register 1 is written by asserting low on CS
, RAS, CAS, WE, high on BA0, low on BA1 and BA2,
while controlling the states of address pins according to the table below.
Mode Register 1
Address Field
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
AL
0*
1
0
*
1
A
14-
1
Rtt_Nom
A0 DLL Enable
0 Enable
1 Disable
* 1 : BA2, A8, A10, A11, A13 and A14 are reserved for future use (RFU) and must be programmed to 0 during MRS.
BA
2
0*
1
A
12
Note : RZQ = 240 ohms
A5 A1 Output Driver Impedance Control
00 RZQ/6
01 RZQ/7
1 0 Reserved
1 1 Reserved
D.I.C
DLL
Note : RZQ = 240 ohms
*3: In Write leveling Mode (MR1[bit7] = 1)
with MR1[bit12] = 1, all RTT_Nom settings
are allowed; in Write Leveling Mode
(MR1[bit7] = 1) with MR1[bit12] = 0, only
RTT_Nom settings of RZQ/2, RZQ/4 and
RZQ/6 are allowed.
*4: If RTT_Nom is used during Writes,
only the values RZQ/2,RZQ/4 and RZQ/6
are allowed.
A9 A6 A2
Rtt_Nom
*3
0 0 0 ODT disabled
001 RZQ/4
010 RZQ/2
011 RZQ/6
100
RZQ/12*
4
101
RZQ/8*
4
1 1 0 Reserved
1 1 1 Reserved
A7 Write leveling enable
0 Disabled
1 Enabled
A4 A3
Additive Latency
0 0 0 (AL disabled)
01 CL-1
10 CL-2
11 Reserved
*2: Outputs disabled - DQs, DQSs, DQSs.
A12
Qoff
*2
0 Output buffer enabled
1
Output buffer disabled
*2
Qoff
Level
0
*
1
Rtt_Nom
D.I.C
Rtt_Nom
BA1 BA0 MRS mode
00 MR0
01 MR1
10 MR2
11 MR3
A
13
0
*
1
AS4C256M16D3B-12BIN
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Rev.1.1 April 2017