Datasheet

AS4C16M32MD1
Confidential 9 Rev. 1.0/July 2014
5. FUNCTION DESCRIPTION
The LPDDR SDRAM is a high speed CMOS, dynamic random-access memory internally configured
as a quad-bank DRAM. These devices contain the following number of bits: 512 Mb has
536,870,912 bits The LPDDR SDRAM uses double data rate architecture to achieve high speed
operation. The double data rate architecture is essentially a 2n prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write
access for the LPDDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data
transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock cycle data
transfers at the I/O pins.
Read and write accesses to the LPDDR SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Accesses
begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the ACTIVE command are used to select the
bank and the row to be accessed. The address bits registered coincident with the READ or WRITE
command are used to select the bank and the starting column location for the burst access.
Prior to normal operation, the LPDDR SDRAM must be initialized. The following section provides
detailed information covering device initialization, register definition, command description and
device operation.
5.1 Initialization
LPDDR SDRAMs must be powered up and initialized in a predefined manner. Operations
procedures other than those specified may result in undefined operation. If there is any
interruption to the device power, the initialization routine should be followed. The steps to be
followed for device initialization are listed below. The Initialization Flow diagram is shown in Figure
4, and the Initialization Flow sequence in Figure 5. The Mode Register and Extended Mode Register
do not have default values. If they are not programmed during the initialization sequence, it may
lead to unspecified operation. The clock stop feature is not available until the device has been
properly initialized from Steps 1 through 11.
1. Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be
brought up simultaneously to prevent device latch-up. Although not required, it is
recommended that VDD and VDDQ are from the same power source. Also assert and hold
Clock Enable (CKE) to a LV-CMOS logic high level
2. Once the system has established consistent device power and CKE is driven high, it is safe to
apply stable clock
3. There must be at least 200 μs of valid clocks before any command may be given to the
DRAM. During this time NOP or DESELECT commands must be issued on the command bus.
4. Issue a PRECHARGE ALL command.
5. Provide NOPs or DESELECT commands for at least tRP time.
6. Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at least
tRFC time. Issue the second AUTO REFRESH command followed by NOPs or DESELECT command
for at least tRFC time. Note as part of the initialization sequence there must be two auto refresh
commands issued. The typical flow is to issue them at Step 6, but they may also be issued
between steps 10 and 11.
7. Using the MRS command, load the base mode register. Set the desired operating modes.
8. Provide NOPs or DESELECT commands for at least tMRD time.