Datasheet

AS4C16M32MD1
Confidential 49 Rev. 1.0/July 2014
8.4 IDD Specification Parameters and Test Conditions
8.4.1 IDD Specification Parameters and Test Conditions,-40°C ~ 85°C
[Recommended Operating Conditions; Notes 1-3]
(512Mb, X32)
PARAMETER
SYMBOL
TEST CONDITION
-5
UNIT
Operating one
tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH; CS is HIGH
bank active-
IDD0
40
mA
between valid commands; address inputs are
pre-charge
current
SWITCHING; data bus inputs are STABLE
Precharge
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin ;
power-down
IDD2P
address and control inputs are SWITCHING; data bus
0.3
mA
standby current
inputs are STABLE
Precharge
all banks idle, CKE is LOW; CS is HIGH, CK = LOW,
power-down
IDD2PS
CK = HIGH; address and control inputs are SWITCHING;
0.3
mA
standby current
with clock stop
data bus inputs are STABLE
Precharge non
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;
10
mA
power-down
IDD2N
address and control inputs are SWITCHING; data bus
standby current
inputs are STABLE
Precharge non
all banks idle, CKE is HIGH; CS is HIGH, CK =
power-down
IDD2NS
LOW, CK = HIGH; address and control inputs are
3
mA
standby current
with clock stop
SWITCHING; data bus inputs are STABLE
Active power-
one bank active, CKE is LOW; CS is HIGH, tCK =
3
mA
down standby
IDD3P
tCKmin; address and control inputs are SWITCHING;
data
current
bus inputs are STABLE
Active power-
one bank active, CKE is LOW; CS is HIGH, CK = LOW,
down standby
IDD3PS
CK = HIGH; address and control inputs are SWITCHING;
3
mA
current with clock
stop
data bus inputs are STABLE
Active non
one bank active, CKE is HIGH; CS is HIGH, tCK =
power-down
IDD3N
tCKmin; address and control inputs are SWITCHING; data
25
mA
standby current
bus inputs are STABLE
Active non
one bank active, CKE is HIGH; CS is HIGH, CK = LOW,
power-down
IDD3NS
CK = HIGH; address and control inputs are SWITCHING;
15
mA
standby current
with clock stop
data bus inputs are STABLE
Operating burst
one bank active; BL = 4; CL = 3; tCK = tCKmin ;
IDD4R
continuous read bursts; IOUT = 0 mA; address inputs are
85
mA
read current
SWITCHING; 50% data change each burst transfer
Operating burst
one bank active; BL = 4; tCK = tCKmin ; continuous write
IDD4W
bursts; address inputs are SWITCHING; 50% data change
65
mA
write current
each burst transfer
Auto-Refresh
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is
IDD5
HIGH; address and control inputs are SWITCHING; data
75
mA
Current
bus inputs are STABLE
Deep Power-
IDD8(4)
Address and control inputs are STABLE; data bus inputs
10
uA
Down current
are STABLE