Datasheet

AS4C16M32MD1
Confidential 45 Rev. 1.0/July 2014
7.13 Deep Power Down
The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside
the LPDDR SDRAM are stopped and all memory data is lost in this mode. All the information in the Mode
Register and the Extended Mode Register is lost.
Deep Power-Down is entered using the BURST TERMINATE command (see Figure 21) except that CKE is
registered Low. All banks must be in idle state with no activity on the data bus prior to entering the DPD
mode. While in this state, CKE must be held in a constant Low state.
To exit the DPD mode, CKE is taken high after the clock is stable and NOP commands must be maintained for
at least 200 μs. After 200 μs a complete re-initialization is required following steps 4 through 11 as defined for
the initialization sequence.
Deep Power-Down entry and exit is shown in Figure 38.