Datasheet

AS4C16M32MD1
Confidential 41 Rev. 1.0/July 2014
7.11 Self Refresh
The SELF REFRESH command (see Figure 34) can be used to retain data in the LPDDR SDRAM, even if the rest
of the system is powered down. When in the Self Refresh mode, the LPDDR SDRAM retains data without
external clocking. The LPDDR SDRAM device has a built-in timer to accommodate Self Refresh operation. The
SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is LOW. Input signals
except CKE are “Don’t Care” during Self Refresh. The user may halt the external clock one clock after the SELF
REFRESH command is registered.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. The clock is internally
disabled during Self Refresh operation to save power. The minimum time that the device must remain in Self Refresh
mode is tRFC.
The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior
to CKE going back High. Once Self Refresh Exit is registered, a delay of at least tXS must be satisfied before a
valid command can be issued to the device to allow for completion of any internal refresh in progress.
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed
when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh an extra AUTO REFRESH
command is recommended.
Figure 36 shows Self Refresh entry and exit.
In the Self Refresh mode, two additional power-saving options exist: Temperature Compensated Self Refresh
(TCSR) and Partial Array Self Refresh (PASR); they are described in the Extended Mode Register section .