Datasheet

AS4C16M32MD1
Confidential 3 Rev. 1.0/July 2014
2. GENERAL DESCRIPTION
This AS4C16M32MD1 is 536,870,912 bits synchronous double data rate Dynamic RAM. Each
134,217,728 bits bank is organized as 8,192 rows by 1024 columns by 16 bits or 8,192 rows by 512
columns by 32bits, fabricated with Alliance Memory’s high performance CMOS technology. This device
uses double data rate architecture to achieve high- speed operation. The double data rate architecture
is essentially 2n-prefetch architecture with an interface designed to transfer two data words per clock
cycle at the I/O balls. Range of operating frequencies, programmable burst lengths and programmable
latencies allow the same device to be useful for a variety of high bandwidth and high performance
memory system applications.
Table 1. Speed Grade Information
Speed Grade – Data rate
Clock Frequency
CAS Latency
t
RCD
(ns)
t
RP
(ns)
400Mbps (max)
200 MHz (max)
3
15
15
Table 2 – Ordering Information for ROHS Compliant Products
Product part No
Org
Temperature
Max Clock (MHz)
Package
AS4C16M32MD1-5BCN
16M x 32
Commercial
(Extended)
-25°C to 85°C
200
90-ball FBGA
AS4C16M32MD1-5BIN
16M x 32
Industrial
-40°C to 85°C
200
90-ball FBGA