Datasheet

AS4C16M32MD1
Confidential 16 Rev. 1.0/July 2014
Violating either of these requirements will result in unspecified operation.
Address bits A0-A2 specify PASR, A3-A4 the TCSR, A5-A6 the Drive Strength. A logic 0 should be
programmed to all the undefined addresses bits to ensure future compatibility.
Reserved states should not be used, as unknown operation or incompatibility with future versions
may result. Address bits A0-A2 specify PASR, A3-A4 the TCSR, A5-A7 the Drive Strength.
A logic 0 should be programmed to all the undefined address bits to ensure future compatibility.
Reserved states should not be used, as unknown operation or incompatibility with future
versions may result.
5.2.2.1 Partial Array Self Refresh
Partial Array Self Refresh (PASR) is an optional feature. With PASR, the self-refresh may be
restricted to a variable portion of the total array. The whole array (default), 1/2 array, or 1/4 array
could be selected. Some vendors may have additional options of 1/8 and 1/16 array refreshed as
well. Data outside the defined area will be lost. Address bits A0 to A2 are used to set PASR.
5.2.2.2 Temperature Compensated Self Refresh
This function can be used in the LPDDR SDRAM to set refresh rates based on case temperature. This
allows the system to control power as a function of temperature. Address bits A3 and A4 are used
to set TCSR.
Some vendors may choose to have Internal Temperature Compensated Self Refresh feature, which
should automatically adjust the refresh rate based on the device temperature without any register
update needed. To maintain backward compatibility, devices having internal TCSR, ignore (don’t
care) the inputs to address bits A3 and A4 during EMRS programming.
5.2.2.3 Output Drive Strength
The drive strength could be set to full or half or three-quarters strength via address bits A5 and A6
and A7.