AS4C16M32MD1 512M (16M x32 bit) Mobile DDR SDRAM Confidential (Rev. 1.0, July. /2014) LPDDR MEMORY 512M (16Mx32bit) Mobile DDR SDRAM Revision History Revision No 1.
AS4C16M32MD1 512M (16M x32 bit) LP Mobile DDR SDRAM Confidential (Rev. 1.0, July. /2014) 1. FEATURES • Density : 512Mbit • Data width: x32 • Power supply : VDD, VDDQ = 1.7 to 1.95V • Speed - Clock frequency : 200MHz (max.) - Data rate : 400Mbps (max.
AS4C16M32MD1 2. GENERAL DESCRIPTION This AS4C16M32MD1 is 536,870,912 bits synchronous double data rate Dynamic RAM. Each 134,217,728 bits bank is organized as 8,192 rows by 1024 columns by 16 bits or 8,192 rows by 512 columns by 32bits, fabricated with Alliance Memory’s high performance CMOS technology. This device uses double data rate architecture to achieve high- speed operation.
AS4C16M32MD1 2.1 Package Pin Configurations Figure 2.2 Pin configurations < Top View > Confidential 4 Rev. 1.
AS4C16M32MD1 2.3 Pin Description CK, CK# (input pins) Clock: The CK and the CK# are the differential clock inputs. All address and control input signals are samples on the crossing of the positive edge of CK and negative edge of CK. Input and output data is referenced to the cross of CK and CK# (both directions of crossing). Internal signals are derived from CK/CK#. CKE (Input pins) Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input buffers and output drivers.
AS4C16M32MD1 DQ for x32 DQ0-DQ31 (I/O) Data Bus: Input / Output DQS for x32:DQS0-DQS3 (I/O) Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered with write data. Used to capture write data. For x32 device, DQS0 corresponds to the data on DQ0-DQ7, DQS1 corresponds to the data on DQ8-DQ15, DQS2 corresponds to the data on DQ16-DQ23, and DQS3 corresponds to the data on DQ24-DQ31.
AS4C16M32MD1 3.0 Mobile DDR SDRAM Addressing Table. ITEM 512 Mb 4 BA0,BA1 A10/AP A0-A12 A0-A8 7.8 Number of banks Bank address pins Auto precharge pin X32 Row addresses Column addresses tREFI(µs) 4. BLOCK DIAGRAM 4.1 Block Diagram Confidential 7 Rev. 1.
AS4C16M32MD1 4.2 Simplified State Diagram Figure 3.1 State Diagram Confidential 8 Rev. 1.
AS4C16M32MD1 5. FUNCTION DESCRIPTION The LPDDR SDRAM is a high speed CMOS, dynamic random-access memory internally configured as a quad-bank DRAM. These devices contain the following number of bits: 512 Mb has 536,870,912 bits The LPDDR SDRAM uses double data rate architecture to achieve high speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.
AS4C16M32MD1 9. Using the MRS command, program the extended mode register for the desired operating modes. Note the order of the base and extended mode register programming is not important. 10. Provide NOP or DESELCT commands for at least tMRD time. 11. The DRAM has been properly initialized and is ready for any valid command. Confidential 10 Rev. 1.
AS4C16M32MD1 5.1.1 Initialization Flow Diagram Confidential 11 Rev. 1.
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AS4C16M32MD1 5.2 Register Definition 5.2.1 Mode Register The Mode Register is used to define the specific mode of operation of the LPDDR SDRAM. This definition includes the definition of a burst length, a burst type, a CAS latency as shown below table. The Mode Register is programmed via the MODE REGISTER SET command (with BA0=0 and BA1=0) and will retain the stored information until it is reprogrammed, the device goes into Deep Power-Down mode, or the device loses power.
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AS4C16M32MD1 Notes: 1. 16-word burst length is optional. 2. For a burst length of two, A1-An selects the two data element block; A0 selects the first access within the block. 3. For a burst length of four, A2-An selects the four data element block; A0-A1 selects the first access within the block. 4. For a burst length of eight, A3-An selects the eight data element block; A0-A2 selects the first access within the block. 5.
AS4C16M32MD1 Violating either of these requirements will result in unspecified operation. Address bits A0-A2 specify PASR, A3-A4 the TCSR, A5-A6 the Drive Strength. A logic 0 should be programmed to all the undefined addresses bits to ensure future compatibility. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. Address bits A0-A2 specify PASR, A3-A4 the TCSR, A5-A7 the Drive Strength.
AS4C16M32MD1 6. COMMANDS All commands (address and control signals) are registered on the positive edge of clock (crossing of CK going high and CK going low). Figure 6 shows basic timing parameters for all commands. Table 5, Table 6 and Table 7 provide a quick reference of available commands. Table 8 and Table 9 provide the current state / next state information. This is followed by a verbal description of each command. Notes: 1. All states and sequences not shown are illegal or reserved. 2.
AS4C16M32MD1 Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of Mobile DDR SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is the result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. DESELECT and NOP are functionally interchangeable. 6.
AS4C16M32MD1 Notes: 1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or Power Down. 2. DESELECT and NOP are functionally interchangeable. 3. All states and sequences not shown are illegal or reserved. 4. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging. 5.
AS4C16M32MD1 10. 11. 12. 13. Once tRP is met, the bank will be in the idle state. Not bank-specific; requires that all banks are idle and no bursts are in progress. Not bank-specific. BURST TERMINATE affects the most recent READ burst, regardless of bank. Requires appropriate DM masking. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ prior to asserting a WRITE command. Notes: 1.
AS4C16M32MD1 For Read with AP, the pre-charge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all the data in the burst. For Write with Auto pre-charge, the pre-charge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the pre-charge period (or tRP) begins.
AS4C16M32MD1 7. OPERATION 7.1. Deselect The DESELECT function (/CS HIGH) prevents new commands from being executed by the Mobile DDR SDRAM. The Mobile DDR SDRAM is effectively deselected. Operations already in progress are not affected. 7.2. No Operation The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to perform a NOP (/CS = LOW, / RAS = /CAS = /WE = HIGH). This prevents unwanted commands from being registered during idle or wait states.
AS4C16M32MD1 7.3 MODE REGISTER The Mode Register and the Extended Mode Register are loaded via the address inputs. See Mode Register and the Extended Mode Register descriptions for further details. The MODE REGISTER SET command (see Figure 8) can only be issued when all banks are idle and no bursts are in progress, and a subsequent executable command cannot be issued until tMRD (see Figure 9) is met.
AS4C16M32MD1 The row remains active until a PRECHARGE command (or READ or WRITE command with Auto Precharge) is issued to the bank. A PRECHARGE command (or READ or WRITE command with Auto Precharge) must be issued before opening a different row in the same bank Confidential 24 Rev. 1.
AS4C16M32MD1 7.5. Read The READ command (see Figure 12) is used to initiate a burst read access to an active row, with a burst length as set in the Mode Register. BA0 and BA1 select the bank, and the address inputs select the starting column location. The value of A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed will be precharged at the end of the read burst; if Auto Precharge is not selected, the row will remain open for subsequent accesses.
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AS4C16M32MD1 7.5.1 Read to Read Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated. The new READ command should be issued X cycles after the first READ command, where X equals the number of desired data-out element pairs (pairs are required by the 2n prefetch architecture). This is shown in Figure 15.
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AS4C16M32MD1 7.5.5 Burst Terminate The BURST TERMINATE command is used to truncate read bursts (with Auto Pre-charge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated. Note that the BURST TERMINATE command is not bank specific. This command should not be used to terminate write bursts. 7.6 Write The WRITE command (see Figure 22) is used to initiate a burst write access to an active row, with a burst length as set in the Mode Register.
AS4C16M32MD1 Figure 23 — Basic Write Timing Parameters During Write bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and the subsequent data elements will be registered on successive edges of DQS. The Low state of DQS between the WRITE command and the first rising edge is called the write preamble, and the Low state on DQS following the last data-in element is called the write postamble.
AS4C16M32MD1 7.6.1 Write to Write Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive edge of the clock following the previous WRITE command. The first data-in element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated.
AS4C16M32MD1 7.6.3 Write to Precharge: Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto Precharge was not activated). To follow a WRITE without truncating the WRITE burst, tWR should be met as shown in Figure 30. Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Figure 31.
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AS4C16M32MD1 7.7 Precharge The PRECHARGE command (see Figure 32) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Confidential 38 Rev. 1.
AS4C16M32MD1 Input A10 determines whether one or all banks are to be precharged. In case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care”. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE command being issued. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging.
AS4C16M32MD1 7.8 Auto Precharge Auto Precharge is a feature which performs the same individual bank pre-charge function as described above, but without requiring an explicit command. This is accomplished by using A10 (A10 = High), to enable Auto Precharge in conjunction with a specific READ or WRITE command. A pre-charge of the bank / row that is addressed with the READ or WRITE command is automatically performed upon completion of the read or write burst.
AS4C16M32MD1 7.11 Self Refresh The SELF REFRESH command (see Figure 34) can be used to retain data in the LPDDR SDRAM, even if the rest of the system is powered down. When in the Self Refresh mode, the LPDDR SDRAM retains data without external clocking. The LPDDR SDRAM device has a built-in timer to accommodate Self Refresh operation. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is LOW. Input signals except CKE are “Don’t Care” during Self Refresh.
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AS4C16M32MD1 7.12 Power Down Power-down is entered when CKE is registered Low (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as pre-charge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE. In power-down mode, CKE Low must be maintained, and all other input signals are “Don’t Care”.
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AS4C16M32MD1 7.13 Deep Power Down The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the LPDDR SDRAM are stopped and all memory data is lost in this mode. All the information in the Mode Register and the Extended Mode Register is lost. Deep Power-Down is entered using the BURST TERMINATE command (see Figure 21) except that CKE is registered Low. All banks must be in idle state with no activity on the data bus prior to entering the DPD mode.
AS4C16M32MD1 7.14 Clock Stop Stopping a clock during idle periods is an effective method of reducing power consumption.
AS4C16M32MD1 8. ELECTRICAL CHARACTERISTIC 8.1 Absolute Maximum Ratings PARAMETER SYMBOL Voltage on VDD relative to VSS VALUES MIN MAX UNITS VDD −0.3 2.7 V Voltage on VDDQ relative to VSS VDDQ −0.3 2.7 V Voltage on any pin relative to VSS VIN, VOUT −0.3 2.7 V Tj -25 -40 85 85 °C Storage Temperature TSTG −55 150 °C Short Circuit Output Current IOUT ±50 mA PD 1.0 W Operating temperature : Power Dissipation 8.
AS4C16M32MD1 8.3 Electrical Characteristics and AC/DC Operating Conditions All values are recommended operating conditions unless otherwise noted. 8.3.1 Electrical Characteristics and AC/DC Operating Conditions (VDD/VDDQ: 1.7~1.95V) PARAMETER/CONDITION Supply Voltage I/O Supply Voltage SYMBOL VDD VDDQ MIN 1.70 1.70 MAX 1.95 1.95 UNITS V V NOTES ADDRESS AND COMMAND INPUTS (A0~An, BA0,BA1,CKE, CS, RAS , CAS , WE ) Input High Voltage VIH 0.8*VDDQ VDDQ + 0.3 V Input Low Voltage VIL −0.3 0.
AS4C16M32MD1 8.4 IDD Specification Parameters and Test Conditions 8.4.
AS4C16M32MD1 Notes: 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate is 1V/ns. 3. Definitions for IDD: LOW is defined as V IN ≤ 0.1 * VDDQ; HIGH is defined as VIN ≥ 0.9 * VDDQ; 4. STABLE is defined as inputs stable at a HIGH or LOW level; SWITCHING is defined as: - Address and command: inputs changing between HIGH and LOW once per two clock cycles; - Data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
AS4C16M32MD1 8.5 AC Timings [Recommended Operating Conditions: Notes 1-9] PARAMETER DQ output access time from CK/ CK SYMBOL CL=3 CL=2 DQS output access time from CL=3 CK/ CK CL=2 tAC tDQSCK Clock low-level width tCH tCL Clock half period tHP Clock high-level width -5 MIN 2.0 2.0 2.0 2.0 0.45 0.45 MAX 5.0 6.5 5.0 6.5 0.55 0.55 Min UNIT NOTES ns ns tCK tCK ns 10,11 tIPW 5 12 0.48 0.58 0.48 0.58 1.4 0.9 1.1 0.9 1.1 2.
AS4C16M32MD1 PARAMETER SYMBOL -5 NOTES ns 24 tCK 25 WRITE recovery time Auto pre-charge write recovery + precharge time tWR tDAL - Internal write to Read command delay tWTR 1 tCK Self-Refresh exit to next valid command delay tXSR 120 ns 26 Exit power down to next valid command delay tXP 2 tCK 27 CKE min. pulse width (high and low pulse width) tCKE 1 tCK Refresh Period Average periodic refresh interval (x16) tREF tREFI MAX UNIT MIN 15 64 7.8 ms μs 28,29 Notes: 1.
AS4C16M32MD1 12. The only time that the clock frequency is allowed to change is during clock stop, power-down or self-refresh modes. 13. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and VIH(DC) to VIL(AC) for falling input signals. 14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. 15. Input slew rate ≥ 1.0 V/ns. 16.
AS4C16M32MD1 8.5.2 Output Slew Rate Characteristics PARAMETER Pull-up and Pull-Down Slew Rate for Full Strength Driver Pull-up and Pull-Down Slew Rate for Three-Quarter Strength Driver Pull-up and Pull-Down Slew Rate for Half Strength Driver Output Slew rate Matching ratio (Pull-up to Pull-down) Notes: 1. Measured with a test load of 20 pF connected to VSSQ. MIN 0.7 0.5 0.3 0.7 MAX 2.5 1.75 1.0 1.4 UNIT V/ns V/ns V/ns - NOTES 1,2 1,2 1,2 3 2.
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AS4C16M32MD1 Alliance Memory Inc. reserves the rights to change the specifications and products without notice. Alliance Memory, Inc., 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 Confidential 58 Rev. 1.
