AS4C16M16SA-C&I Revision History Revision Rev 1.0 Rev 2.0 Rev 3.0 Details Preliminary datasheet Correct some typing mistakes. 1. Add AS4C16M16SA-6TCN part. 2. Modify ordering information. 3. Add part number system on the last page. Date February 2014 March 2014 March 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. Confidential 0 Rev. 3.0 Mar.
AS4C16M16SA-C&I 256M – (16Mx16bit) Synchronous DRAM (SDRAM) Confidential Advanced(Rev. 3.0, Mar. /2015) Features Overview The 256Mb SDRAM is a high-speed CMOS synchronous DRAM containing 256 Mbits. It is internally configured as 4 Banks of 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK).
AS4C16M16SA-C&I Figure 1. Pin Assignment (Top View) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE# CAS# RAS# CS# BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS Figure 1.
AS4C16M16SA-C&I Figure 2.
AS4C16M16SA-C&I Table 3. Pin Details Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
AS4C16M16SA-C&I DQ0-DQ15 Input / Output NC - VDDQ Supply Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK. The I/Os are maskabled during Reads and Writes. No Connect: These pins should be left unconnected. DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3V 0.3V ) VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. (0V) VDD Supply Power Supply: +3.3V 0.
AS4C16M16SA-C&I Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 4 shows the truth table for the operation commands. Table 4.
AS4C16M16SA-C&I Commands 1 BankActivate (RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A12 = Row Address) The BankActivate command activates the idle bank designated by the BA0, 1 signals. By latching the row address on A0 to A12 at the time of this command, the selected row access is initiated. The read or write operation in the same bank can occur after a time delay of tRCD(min.) from the time of bank activation.
AS4C16M16SA-C&I T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP CAS# Latency=2 tCK2, DQ NOP DOUT A0 CAS# Latency=3 tCK3, DQ NOP NOP NOP NOP DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 NOP NOP DOUT A3 Figure 4. Burst Read Operation (Burst Length = 4, CAS# Latency = 2, 3) The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e. DQM latency is two clocks for output buffers).
AS4C16M16SA-C&I T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND NOP NOP READ A NOP NOP CAS# Latency=2 tCK2, DQ WRITE B NOP NOP NOP DIN B0 DIN B1 DIN B2 DIN B3 Must be Hi-Z before the Write Command Don’t Care Figure 7.
AS4C16M16SA-C&I 5 Read and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A8 = Column Address) The Read and AutoPrecharge command automatically performs the precharge operation after the read operation. Once this command is given, any subsequent command cannot occur within a time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge function is ignored.
AS4C16M16SA-C&I T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP WRITE A READ B CAS# Latency=2 tCK2, DQ DIN A0 don’t care CAS# Latency=3 tCK3, DQ DIN A0 don’t care NOP NOP NOP DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 don’t care NOP NOP NOP DOUT B3 Input data must be removed from the DQ at least one clock cycle before the Read data appears on the outputs to avoid data contention Figure 12.
AS4C16M16SA-C&I T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CLK Bank A Activate COMMAND NOP NOP WRITE A Auto Precharge NOP NOP NOP NOP NOP Bank A Activate tDAL DQ DIN A0 DIN A1 tDAL=tWR+tRP Begin AutoPrecharge Bank can be reactivated at completion of tDAL Figure 14. Burst Write with Auto-Precharge (Burst Length = 2) 8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A12 = Register Data) The mode register stores the data for controlling the various operating modes of SDRAM.
AS4C16M16SA-C&I T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK CKE tMRD CS# RAS# CAS# WE# BA0,1 A10 Address Key A0-A9, A11-A12 DQM DQ tRP Hi-Z PrechargeAll Mode Register Set Command Don’t Care Any Command Figure 15. Mode Register Set Cycle Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8, or full page. Table 6.
AS4C16M16SA-C&I Burst Definition, Addressing Sequence of Sequential and Interleave Mode Table 8.
AS4C16M16SA-C&I Write Burst Length (A9) This bit is used to select the write burst mode. When the A9 bit is "0", the Burst-Read-Burst-Write mode is selected. When the A9 bit is "1", the Burst-Read-Single-Write mode is selected. Table 11. Write Burst Length A9 Write Burst Mode 0 Burst-Read-Burst-Write 1 Burst-Read-Single-Write Note: A10 and BA0, 1 should stay “L” during mode set cycle.
AS4C16M16SA-C&I 11 Device Deselect command (CS# = "H") The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No Operation command. 12 AutoRefresh command (RAS# = "L", CAS# = "L", WE# = "H", CKE = "H", A0-A12 = Don't care) The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-before-RAS# (CBR) Refresh in conventional DRAMs.
AS4C16M16SA-C&I Table 12. Absolute Maximum Rating Symbol Item Rating VIN, VOUT Input, Output Voltage -1.0 ~ 4.6 V 1 VDD, VDDQ Power Supply Voltage -1.0 ~ 4.6 V 1 Commercial 0 ~ 70 °C 1 Industrial -40 ~ 85 °C 1 TA Ambient Temperature Unit Note TSTG Storage Temperature -55 ~ 150 °C 1 TSOLDER Soldering Temperature (10 second) 260 °C 1 PD Power Dissipation 1 W 1 IOS Short Circuit Output Current 50 mA 1 Table 13. Recommended D.C.
AS4C16M16SA-C&I Table 15. D.C. Characteristics (VDD = 3.3V 0.
AS4C16M16SA-C&I Table 16. Electrical Characteristics and Recommended A.C. Operating Conditions (VDD = 3.3V±0.3V, TA = -40~85°C) (Note: 5, 6, 7, 8) Symbol tRC tRFC tRCD tRP tRRD tMRD tRAS tWR -6 A.C. Parameter -7 Min. Max. Min. Max.
AS4C16M16SA-C&I Table 17. LVTTL Interface Reference Level of Output Signals 1.4V / 1.4V Output Load Reference to the Under Output Load (B) Input Signal Levels 2.4V / 0.4V Transition Time (Rise and Fall) of Input Signals 1ns Reference Level of Input Signals 1.4V 1.4V 3.3V 50Ω 1.2KΩ Output Output 30pF Z0=50Ω 870Ω Figure 18.1 LVTTL D.C. Test Load (A) 30pF Figure 18.2 LVTTL A.C. Test Load (B) 7. Transition times are measured between VIH and VIL.
AS4C16M16SA-C&I Timing Waveforms Figure 19.
AS4C16M16SA-C&I Figure 20.
AS4C16M16SA-C&I Figure 21. Auto Refresh (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11-A12 RAx tRP tRC tRC CAx tRCD DQM DQ Ax0 Precharge All Command Auto Refresh Command Auto Refresh Command Activate Command Bank A Ax1 Read Command Bank A Don’t Care Confidential 23 Rev. 3.0 Mar.
AS4C16M16SA-C&I Figure 22.
AS4C16M16SA-C&I Figure 23. Self Refresh Entry & Exit Cycle T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CLK *Note 2 CKE tXSR *Note 5 *Note 1 *Note 3,4 *Note 8 tPDE tIS tIH *Note 6 tIS *Note 7 CS# RAS# *Note 9 CAS# WE# BA0,1 A10 A0-A9, A11-A12 DQM DQ Hi-Z Hi-Z Self Refresh Exit Self Refresh Entry Auto Refresh Don’t Care Note: To Enter SelfRefresh Mode 1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle. 2.
AS4C16M16SA-C&I Figure 24.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11-A12 RAx CAx DQM DQ tHZ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Clock Suspend 1 Cycle Ax2 Clock Suspend 2 Cycles Ax3 Clock Suspend 3 Cycles Don’t Care Confidential 26 Rev. 3.0 Mar.
AS4C16M16SA-C&I Figure 24.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11-A12 RAx CAx DQM DQ tHZ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Ax3 Clock Suspend 3 Cycles Don’t Care Confidential 27 Rev. 3.0 Mar.
AS4C16M16SA-C&I Figure 25. Clock Suspension During Burst Write (Using CKE) (Burst Length=4) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11-A12 RAx CAx DQM DQ Hi-Z DAx0 Activate Command Bank A Confidential DAx1 Clock Suspend 1 Cycle Write Command Bank A DAx2 Clock Suspend 2 Cycles DAx3 Clock Suspend 3 Cycles Don’t Care 28 Rev. 3.0 Mar.
AS4C16M16SA-C&I Figure 26.
AS4C16M16SA-C&I Figure 27.1.
AS4C16M16SA-C&I Figure 27.2.
AS4C16M16SA-C&I Figure 28.
AS4C16M16SA-C&I Figure 29.1.
AS4C16M16SA-C&I Figure 29.2.
AS4C16M16SA-C&I Figure 30.
AS4C16M16SA-C&I Figure 31.1.
AS4C16M16SA-C&I Figure 31.2.
AS4C16M16SA-C&I Figure 32.1.
AS4C16M16SA-C&I Figure 32.2.
AS4C16M16SA-C&I Figure 33.
AS4C16M16SA-C&I Figure 34.1.
AS4C16M16SA-C&I Figure 34.2.
AS4C16M16SA-C&I Figure 35.
AS4C16M16SA-C&I Figure 36.1.
AS4C16M16SA-C&I Figure 36.2.
AS4C16M16SA-C&I Figure 37.
AS4C16M16SA-C&I Figure 38.
AS4C16M16SA-C&I Figure 39.
AS4C16M16SA-C&I Figure 40.
AS4C16M16SA-C&I Figure 41.
AS4C16M16SA-C&I Figure 42.
AS4C16M16SA-C&I Figure 43. 54 Pin TSOP II Package Outline Drawing Information Symbol A A1 A2 B C D E e HE L L1 S y θ Confidential Dimension in inch Min Nom Max --0.002 0.035 0.01 0.004 0.87 0.395 --0.455 0.016 ----0° ----0.039 0.014 0.006 0.875 0.400 0.031 0.463 0.02 0.032 0.028 ----- 0.047 0.008 0.043 0.018 0.008 0.88 0.405 --0.471 0.024 ----0.004 8° Dimension in mm Min Nom Max --0.05 0.9 0.25 0.12 22.09 10.03 --11.56 0.4 ------0° 52 ----1.0 0.35 0.165 22.22 10.16 0.8 11.76 0.5 0.84 0.71 ----- 1.
AS4C16M16SA-C&I Figure 44. 54 Ball TFBGA Package Outline Drawing Information A1 INDEX Bottom View TOP View Side View Symbol A A1 A2 D E D1 E1 e b F Confidential Dimension in inch Min Nom Max --0.047 0.010 0.012 0.014 -0.033 -0.311 0.315 0.319 0.311 0.315 0.319 -0.252 --0.252 --0.031 -0.016 0.018 0.020 -0.126 -- 53 Dimension in mm Min Nom Max --1.20 0.25 0.30 0.35 -0.85 -7.90 8.00 8.10 7.90 8.00 8.10 -6.40 --6.40 --0.80 -0.40 0.45 0.50 -3.20 -- Rev. 3.0 Mar.
AS4C16M16SA-C&I PART NUMBERING SYSTEM AS4C DRAM 16M16SA 16M16=16Mx16 SA=SDRAM（A version） 6/7 T/B 6=166MHz 7=143MHZ T = TSOP II B = FBGA C/I C=Commercial (0° C ～ 70° C) I=Industrial (-40° C ～ 85° C) N Indicates Pb and Halogen Free Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved.
