Datasheet

Figure 23 — Basic Write Timing Parameters
During Write bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE
command, and the subsequent data elements will be registered on successive edges of DQS. The Low state of DQS between
the WRITE command and the first rising edge is called the write preamble, and the Low state on DQS following the last data-in
element is called the write postamble.
The time between the WRITE command and the first corresponding rising edge of DQS (t
DQSS) is specified with a relatively
wide range - from 75% to 125% of a clock cycle. Figure 24 shows the two extremes of t
DQSS for a burst of 4. Upon completion
of a burst, assuming no other commands have been initiated, the DQs will remain high-Z and any additional input data will be
ignored.
AS4C16M16MD1
256Mb MOBILE DDR SDRAM
Confidential
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Ver.1.1 Oct.2015