Datasheet

BA1 BA0 A[n]~A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 Reserved
Drive Strength
000b: Full
Strength Driver
001b: Half
Strength Driver
010b:Quarter
Strength Driver
011b:Octant
Strength Driver
100b:ThreeQuarters
Strength Driver
Reserved
PASR
000b : All banks
001b : 1/2 array(BA1=0)
010b : ¼ array(BA1=BA0=0)
101b : 1/8 array
(BA1 = BA0 = Row Addr MSB = 0)
110b : 1/16 array
(BA1=BA0 = Row Addr 2 MSB = 0)
5.2.2.1 Partial Array Self Refresh
Partial Array Self Refresh (PASR) is an optional feature. With PASR, the self refresh may be restricted to a variable portion of
the total array. The whole array (default), 1/2 array, or 1/4 array could be selected. Some vendors may have additional options of
1/8 and 1/16 array refreshed as well. Data outside the defined area will be lost. Address bits A0 to A2 are used to set PASR.
5.2.2.2 Temperature Compensated Self Refresh
This function can be used in the LPDDR SDRAM to set refresh rates based on case temperature.This allows the system to
control power as a function of temperature. Address bits A3 and A4 are used to set TCSR.
Some vendors may choose to hav
e Internal Temperature Compensated Self Refresh feature, which should automatically adjust
the refresh rate based on the device temperature without any register update needed. To maintain backward compatibility,
devices having internal TCSR, ignore (don’t care) the inputs to address bits A3 and A4 during EMRS programming.
5.2.2.3 Output Drive Strength
The drive strength could be set to full or half or three-quarters strength via address bits A5 and A6 and A7. The I-V curves for
the full drive strength and half drive strength and three-quarters drive strength are included in this document (cf. Table 17 and
Table 18, Figure 45 and Figure 46 and Figure 47).
AS4C16M16MD1
256Mb MOBILE DDR SDRAM
Confidential
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Ver.1.1 Oct.2015