Datasheet

Timing of WR command to Power-down
entry (BL8OTF, BL8MRS, BL4OTF)
t
WRPDEN
(min)
WL + 4 + [tWR/tCK(avg)] nCK
9
Timing of WR command to Power-down
entry (BC4MRS)
t
WRPDEN
(min)
WL + 2 + [tWR/tCK(avg)] nCK
9
Timing of WRA command to Power-down
entry (BL8OTF, BL8MRS, BL4OTF)
t
WRAPDEN
WL+4
+WR+1
-
nCK
10
Timing of WRA command to Power-down
entry (BC4MRS)
t
WRAPDEN
WL+2
+WR+1
-
nCK
10
Timing of REF command to Power-down
entry
t
REFPDEN
1
-
nCK
20,21
Timing of MRS command to Power-down
entry
t
MRSPDEN
t
MOD
(min)
-
RTT turn-on t
AON
-225 225 ps
7
Asynchronous RTT turn-on delay
(Power-down with DLL frozen)
t
AONPD
2 8.5 ns
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
t
AOF
0.3 0.7 t
CK
(avg)
8
Asynchronous RTT turn-off delay
(Power-down with DLL frozen)
t
AOFPD
2 8.5 ns
ODT high time without write command
or with write command and BC4
ODTH4
4
-
nCK
ODT high time with Write command
and BL8
ODTH8
6
-
nCK
RTT dynamic change skew t
ADC
0.3 0.7 t
CK
(avg)
Power-up and reset calibration time t
ZQinit
512 - nCK
Normal operation full calibration time t
ZQoper
256 - nCK
Normal operation short calibration time t
ZQCS
64 - nCK
23
First DQS pulse rising edge after write
leveling mode is programmed
t
WLMRD
40
-
nCK
3
DQS, DQS delay after write leveling
mode is pro-grammed
t
WLDQSEN
25
-
nCK
3
Write leveling setup time from rising CK,
CK
crossing to rising DQS, DQS crossing
t
WLS
165
-
ps
Write leveling hold time from rising DQS,
DQS
crossing to rising CK, CK crossing
t
WLH
165
-
ps
Write leveling output delay t
WLO
0 7.5 ns
Write leveling output error t
WLOE
0 2 ns
Absolute clock period t
CK
(abs)
tCK(avg)min +
tJIT(per)min
tCK(avg)max +
tJIT(per)max
ps
Absolute clock high pulse width t
CH
(abs) 0.43 - t
CK
(avg)
30
Absolute clock low pulse width t
CL
(abs) 0.43 - t
CK
(avg)
31
Clock period jitter t
JIT
(per) -70 70 ps
Clock period jitter during DLL locking
period
t
JIT
(per,lck) -60 60 ps
Parameter Symbol
- 12 (DDR3L-1600)
Unit NoteMin Max
AS4C128M16D3LB-12BCN
Confidential
- 40/45 -
Rev.1.0 Mar 2016