Datasheet

DDR3L-1600 Speed Bins
Speed Bin
- 12 (DDR3L-1600)
Unit Notes
CL-nRCD-nRP 11-11-11
Parameter Symbol Min Max
Internal read command to first data tAA 13.75
(13.125)
20 ns
7
Active to read or write delay time tRCD 13.75
(13.125)
-ns
7
Precharge command period tRP 13.75
(13.125)
-ns
7
Active to active/auto-refresh command time tRC 48.75
(48.125)
-ns
7
Active to precharge command period tRAS 35 9 * tREFI ns
6
Average Clock
Cycle Time
CL = 5 CWL = 5 tCK(avg) 3.0 3.3 ns
1,2,3,5
CWL = 6,7 tCK(avg) Reserved Reserved ns 4
CL = 6 CWL = 5 tCK(avg) 2.5 3.3 ns
1,2,3,5
CWL = 6 tCK(avg) Reserved Reserved ns 4
CWL = 7 tCK(avg) Reserved Reserved ns 4
CL = 7 CWL = 5 tCK(avg) Reserved Reserved ns 4
CWL = 6 tCK(avg) 1.875 < 2.5 ns
1,2,3,5
CWL = 7 tCK(avg) Reserved Reserved ns 4
CL = 8 CWL = 5 tCK(avg) Reserved Reserved ns 4
CWL = 6 tCK(avg) 1.875 < 2.5 ns
1,2,3,5
CWL = 7 tCK(avg) Reserved Reserved ns 4
CL = 9 CWL = 5, 6 tCK(avg) Reserved Reserved ns 4
CWL = 7 tCK(avg) 1.5 1.875 ns
1,2,3,5
CL = 10 CWL = 5, 6 tCK(avg) Reserved Reserved ns 4
CWL = 7 tCK(avg) 1.5 1.875 ns
1,2,3,5
CWL = 8 tCK(avg) Reserved Reserved ns 4
CL = 11 CWL = 5, 6,7 tCK(avg) Reserved Reserved ns 4
CWL = 8 tCK(avg) 1.25 1.5 ns 1,2,3
Supported CL setting 5, 6, 7, 8, 9, 10,11 nCK
Supported CWL setting 5, 6, 7, 8 nCK
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE
7. CDI_CTRL applies to ODT, CS and CKE
8.
CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9.
CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
AS4C128M16D3LB-12BCN
Confidential
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Rev.1.0 Mar 2016