Datasheet

Input/Output Capacitance
Parameter
Symbol
DDR3L-1600
Units NOTE
Min Max
1.35V
Input/output capacitance
(DQ, DM, DQS, DQS
, TDQS, TDQS)
CIO
1.2 2.3 pF 1,2,3
Input capacitance
(CK and CK
)
CCK 0.8 1.4
pF 2,3
Input capacitance delta
(CK and CK
)
CDCK 0 0.15 pF 2,3,4
Input capacitance
(All other input-only pins)
CI 0.75 1.3 pF 2,3,6
Input capacitance delta
(DQS and DQ
S
)
CDDQS 0 0.15 pF 2,3,5
Input capacitance delta
(All control input-only pins)
CDI_CTRL -0.4 0.2 pF 2,3,7,8
Input capacitance delta
(all ADD and CMD
input-only p
ins)
CDI_ADD_CMD -0.4 0.4 pF 2,3,9,10
Input/output capacitance delta
(DQ, DM, DQS, DQS
, TDQS, TDQS)
CDIO -0.5 0.3 pF 2,3,11
Input/output capacitance of ZQ pin CZQ - 3 pF 2,3,12
1.5V
Input/output capacitance
(DQ, DM, DQS, DQS
, TDQS, TDQS)
CIO 1.4 2.3 pF 1,2,3
Input capacitance
(CK and CK
)
CCK 0.8 1.4 pF 2,3
Input capacitance delta
(CK and CK
)
CDCK 0 0.15 pF 2,3,4
Input capacitance
(All other input-only pins)
CI 0.75 1.3 pF 2,3,6
Input capacitance delta
(DQS and DQ
S
)
CDDQS 0 0.15 pF 2,3,5
Input capacitance delta
(All control input-only pins)
CDI_CTRL -0.4 0.2 pF 2,3,7,8
Input capacitance delta
(all ADD and CMD
input-only p
ins)
CDI_ADD_CMD -0.4 0.4 pF 2,3,9,10
Input/output capacitance delta
(DQ, DM, DQS, DQS
, TDQS, TDQS)
CDIO -0.5 0.3 pF 2,3,11
Input/output capacitance of ZQ pin CZQ - 3 pF 2,3,12
NOTE :
1. Although the DM pin has different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is mea-
sured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK
ANALYZER( VNA)") with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE,
RESET
and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
AS4C128M16D3LB-12BCN
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Rev.1.0 Mar 2016