Datasheet

NOTE :
1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
Operating Burst Read Current; CKE: High; External clock: On; tCK, CL: see
timing used table; BL: 8; AL:
0; CS: High between RD; Command, Address:
partially toggling; Data IO: seamless read data burst with different data be-
tween one burst and the next one; DM: stable at 0; Bank Activity: all banks
open, RD commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and
RTT: Enabled in Mode Registers; ODT Signal: stable at 0
IDD4R
150
mA
Operating Burst Write Current; CKE: High; External clock: On; tCK, CL: see
timing used table; BL: 8; AL:
0; CS: High between WR; Command, Address:
partially toggling; Data IO: seamless write data burst with different data be-
tween one burst and the next one; DM: stable at 0; Bank Activity: all banks
open, WR commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and
RTT: Enabled in Mode Registers; ODT Signal: stable at HIGH
IDD4W
155
mA
Burst Refresh Current; CKE: High; External clock: On; tCK, CL, nRFC: see
timing used table; BL: 8; AL: 0; CS
: High between REF; Command, Address:
partially toggling; Data IO: FLOATING; DM:stable at 0; Bank Activity: REF
command every nRFC; Output Buffer and RTT: Enabled in Mode Registers;
ODT Signal: stable at 0
IDD5B
135
mA
Self Refresh Current: Normal Temperature Range; TCASE: 0- 85°C; Auto
Self-Refresh (ASR): Disabled; Self-Refresh Temperature Range (SRT): Nor-
mal; CKE: Low; External clock: Off; CK and CK
: LOW; CL: see timing used ta-
ble; BL: 8; AL: 0; CS
, Command, Address, Data IO: FLOATING; DM: stable at
0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in
Mode Registers; ODT Signal: FLOATING
IDD6
12
mA
Self Refresh Current: Extended Temperature Range; TCASE: 0- 95°C;
Auto Self-Refresh (ASR): Disabled; Self-Refresh Temperature Range (SRT):
Extended; CKE: Low; External clock: Off; CK and CK
: LOW; CL: see timing
used table; BL: 8; AL: 0; CS
, Command, Address, Data IO: FLOATING; DM:
stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Out-
put Buffer and RTT: Enabled in Mode Registers; ODT Signal: FLOATING
IDD6ET
14
mA
Operating Bank Interleave Read Current; CKE: High; External clock: On;
tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see timing used table; BL: 8; AL:
CL-1; CS: High between ACT and RDA; Command, Address: partially toggling;
Data IO: read data bursts with different data between one burst and the next
one; DM: stable at 0; Bank Activity: two times interleaved cycling through
banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in
Mode Registers; ODT Signal: stable at 0
IDD7
220
mA
RESET Low Current; RESET: Low; External clock: off; CK and CK: LOW;
CKE: FLOATING; CS, Command, Address, Data IO: FLOAT
ING; ODT Signal
: FLOATING
IDD8
13
mA
Conditions Symbol
IDD max.
Unit
5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
6)
Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM
7) Read Burst type : Nibble Sequential, set MR0 A[3]=0B
AS4C128M16D3LB-12BCN
Confidential
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Rev.1.0 Mar 2016