Datasheet

Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS(1.5V)
NOTE:1.Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become
equal to or less than VIL(ac) level.
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, CK
, DQS) has also to comply with certain
requirements for single-ended signals.
CK and CK
have to approximately reach VSEH min / VSEL max [ approximately equal to the AC-levels
( VIH(AC) / VIL(AC) ) for Address/command signals ] in every half-cycle.
DQS, DQS
have to reach VSEH min / VSEL max [ approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ
signals ] in every half-cycle proceeding and following a valid transition.
Note that the applicable AC-levels for Address/command and DQ’s might be different per speed-bin etc.
E.g. if VIH150(AC) / VIL150(AC) is used for Address/command signals, then these AC-levels apply also for
the single-ended components of differential CK and CK
.
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV
Min.
Max.
> 4.0
75
-
4.0
57
-
3.0
50
-
2.0
38
-
1.8
34
-
1.6
29
-
1.4
22
-
1.2
13
-
1.0
0
-
< 1.0
0
-
AS4C128M16D3LB-12BCN
Confidential
- 23/45 -
Rev.1.0 Mar 2016
tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV
Min.
Max.
175
-
170
-
167
-
163
-
162
-
161
-
159
-
155
-
150
-
150
-