Datasheet
Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, RTT_WR impedance and
CAS write latency (CWL). The Mode Register 2 is written by asserting low on CS
, RAS, CAS, WE, high on
BA1, low on BA0 and BA2, while controlling the states of address pins according to the table below.
Mode Register 2
Address Field
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1 0*
1
BA
2
0*
1
* 1 : BA2, A0 ~ A2, A8, A11 ~ A14 are RFU and must be programmed to 0 during MRS.
* 2 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled.
During write leveling, Dynamic ODT is not available.
SRT
A7 Self-refresh temperature range (SRT)
0 Normal operating temperature range
1 Extend temperature self-refresh (Optional)
0*
1
Rtt_WR
A10 A9
Rtt_WR
*2
00
Dynamic ODT off
(Write does not affect Rtt value)
01 RZQ/4
10 RZQ/2
11 Reserved
BA1 BA0 MRS mode
00 MR0
01 MR1
10 MR2
11 MR3
0
CWLASR
A6
Auto Self-refresh (ASR)
0
1 ASR enable (Optional)
Manual SR Reference (SRT)
A
14 -
A5 A4 A3 CAS write Latency (CWL)
000 5 (tCK(avg) ≥ 2.5ns)
0 0 1 6 (2.5ns >tCK(avg) ≥ 1.875ns)
0 1 0 7 (1.875ns>tCK(avg) ≥ 1.5ns)
011 8 (1.5ns>tCK(avg) ≥ 1.25ns)
101
1 1 0 Reserved
1 1 1 Reserved
1 0 0 9 (1.25ns tCK(avg)
1.07ns)
≥
>
10 (1.07ns tCK(avg)
0.935ns)
≥
>
0*
1
AS4C128M16D3LB-12BCN
Confidential
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Rev.1.0 Mar 2016