Datasheet

Figure 11. ODT update delay timing-tMOD
CK
Updating
Rtt
t
IS
EMRS NOP
NOP
NOP
NOP
NOP
CMD
t
AOFD
t
MOD, max
t
MOD, min
Old setting New setting
ODT
NOTE 1: To prevent any impedance glitch on the channel, the following conditions must be met:
- t
AOFD
must be met before issuing the EMRS command.
- ODT must remain LOW for the entire duration of t
MOD
window, until t
MOD
, max is met.
then the ODT is ready for normal operation with the new setting, and the ODT signal may be raised again to turned
on the ODT.
NOTE 2: EMRS command directed to EMR(1), which updates the information in EMR(1)[
A6,A2], i.e. Rtt (Nominal).
NOTE 3: "setting" in this diagram is the Register and I/O setting, not what is measured from outside.
CK#
Figure 12. ODT update delay timing-t
MOD
, as measured from outside
CK#
CK
Rtt
t
IS
EMRS
CMD
t
AOFD
t
MOD, max
Old setting
New setting
ODT
NOP
NOP NOP NOP NOP
t
AOND
NOTE 1: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).
NOTE 2: "setting" in this diagram is measured from outside.
AS4C128M16D2A-25BCN
AS4C128M16D2A-25BIN
Confidential
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Rev.1.0 Dec 2015