Datasheet
Table 26. IDD specification parameters and test conditions
(V
DD
= 1.8V ± 0.1V, T
OPER
= -40~95 °C)
Parameter & Test Condition
Symbol
-25
Unit
Max.
Operating one bank active-precharge current:
t
CK
=t
CK
(min), t
RC
= t
RC
(min), t
RAS
= t
RAS
(min); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
I
DD0
130
mA
Operating one bank active-read-precharge current:
I
OUT
= 0mA; BL = 4, CL = CL (min), AL = 0; t
CK
= t
CK
(min),t
RC
= t
RC
(min),
t
RAS
= t
RAS
(min), t
RCD
= t
RCD
(min);CKE is HIGH, CS# is HIGH between valid
commands;Address bus inputs are switching; Data pattern is same as I
DD4W
I
DD1
150
mA
Precharge power-down current:
All banks idle;t
CK
=t
CK
(min); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
I
DD2P
16
mA
Precharge quiet standby current:
All banks idle; t
CK
=t
CK
(min); CKE is HIGH, CS# is HIGH; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
I
DD2Q
70
mA
Precharge standby current:
All banks idle; t
CK
= t
CK
(min); CKE is HIGH, CS# is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
I
DD2N
70
mA
Active power-down current:
All banks open; t
CK
=t
CK
(min); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
MRS(A12)=0
I
DD3P
46
mA
MRS(A12)=1
32
mA
Active standby current:
All banks open; t
CK
= t
CK
(min), t
RAS
= t
RAS
(max), t
RP
= t
RP
(min); CKE is
HIGH, CS# is HIGH between valid commands; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
I
DD3N
90
mA
Operating burst write current:
All banks open,continuous burst writes; BL = 4, CL = CL (min), AL = 0; t
CK
=
t
CK
(min), t
RAS
= t
RAS
(max), t
RP
= t
RP
(min); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are switching; Data bus
inputs are switching
I
DD4W
180
mA
Operating burst read current:
All banks open, continuous burst reads, I
OUT
= 0mA; BL = 4, CL = CL (min),
AL = 0; t
CK
= t
CK
(min), t
RAS
= t
RAS
(max), t
RP
= t
RP
(min); CKE is HIGH, CS#
is HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
I
DD4R
180
mA
Burst refresh current:
t
CK
= t
CK
(min); refresh command at every t
RFC
(min) interval; CKE is HIGH,
CS# is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
I
DD5
290
mA
Self refresh current:
CK and CK# at 0V; CKE ≤ 0.2V;Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
I
DD6
12
mA
Operating bank interleave read current:
All bank interleaving reads, I
OUT
= 0mA; BL = 4, CL = CL (min), AL =t
RCD
(min) - 1 x t
CK
(min); t
CK
= t
CK
(min), t
RC
= t
RC
(min), t
RRD
= t
RRD
(min), t
RCD
=
t
RCD
(min); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are STABLE during DESELECTs.Data pattern is same as IDD4R
I
DD7
330
mA
NOTE 1: IDD specifications are tested after the device is properly initialized.
NOTE 2: Input slew rate is specified by AC Parametric Test Condition.
NOTE 3: IDD parameters are specified with ODT disabled.
NOTE 4: Data bus consists of DQ, DM, LDQS, LDQS#, UDQS and UDQS#. IDD values must be met with all combinations of
EMRS bits 10 and 11.
NOTE 5: LOW = VIN VILAC(max), HIGH = VIN VIHAC(min), STABLE = inputs stable at a HIGH or LOW level, FLOATING =
inputs at VREF = VDDQ/2, SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per
two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once
per clock) for DQ signals not including masks or strobes.
AS4C128M16D2A-25BCN
AS4C128M16D2A-25BIN
Confidential
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Rev.1.0 Dec 2015