Datasheet

Overview
The 2Gb DDR2 is a high-speed CMOS Double-Data-
Rate-Two (DDR2), synchronous dynamic random -
access memory (SDRAM) containing 2048 Mbits in a 16-
bit wide data I/Os. It is internally configured as a 8-bank
DRAM, 8 banks x 16Mb addresses x 16 I/Os. The device
is designed to comply with DDR2 DRAM key features
such as posted CAS# with additive latency, Write latency
= Read latency -1, Off-Chip Driver (OCD) impedance
adjustment, and On Die Termination(ODT).
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks. Inputs
are latched at the cross point of differential clocks (CK
rising and CK# falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS#) in a source
synchronous fashion. The address bus is used to convey
row, column, and bank address information in RAS #,
CAS# multiplexing style. Accesses begin with the
registration of a Bank Activate command, and then it is
followed by a Read or Write command. Read and write
accesses to the DDR2 SDRAM are 4 or 8-bit burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Operating the eight memory
banks in an interleaved fashion allows random access
operation to occur at a higher rate than is possible with
standard DRAMs. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. A sequential
and gapless data rate is possible depending on burst
length, CAS latency, and speed grade of the device.
Features
•
JEDEC Standard Compliant
•
JEDEC standard 1.8V I/O (SSTL_18-compatible)
•
Power supplies: V
DD
& V
DDQ
= +1.8V ± 0.1V
•
Operating temperature:
- Commercial (0 ~ 85 °C)
- Industrial (-40 ~ 95 °C)
•
Supports JEDEC clock jitter specification
•
Fully synchronous operation
•
Fast clock rate: 400MHz
•
Differential Clock, CK & CK#
•
Bidirectional single/differential data strobe
- DQS & DQS#
•
8 internal banks for concurrent operation
•
4-bit prefetch architecture
•
Internal pipeline architecture
•
Precharge & active power down
•
Programmable Mode & Extended Mode registers
•
Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5
•
WRITE latency = READ latency - 1 t
CK
•
Burst lengths: 4 or 8
•
Burst type: Sequential / Interleave
•
DLL enable/disable
•
Off-Chip Driver (OCD)
- Impedance Adjustment
- Adjustable data-output drive strength
•
On-die termination (ODT)
•
RoHS compliant
•
Auto Refresh and Self Refresh
•
8192 refresh cycles / 64ms
- Average refresh period
7.8µs @ -40°C ≦TC≦ +85°C
3.9µs @ +85°C ＜TC≦ +95°C
• Package: 84-ball 8 x 12.5 x 1.2mm (max) FBGA
- Pb Free and Halogen Free
Table 2. Ordering Information
Product part No
Org Temperature
Max Clock (MHz)
AS4C128M16D2A-25BCN
400
Package
84-ball FBGA
AS4C128M16D2A-25BCN
AS4C128M16D2A-25BIN
Confidential
- 2/63 -
Rev.1.0 Dec 2015
AS4C128M16D2A-25BIN
128Mx 16
Commercial 0°C to 85°C
128Mx 16
Industrial
-40°C to 95°C
400
84-ball FBGA
Table 1. Speed Grade Information
Speed Grade
Clock Frequency
CAS Latency
tRCD(ns)
DDR2-800
12.5
tRP(ns)
12.5
400MHz
5