User`s guide

109

GND

DC (Debug Clock)

RESETn

DD (Debug Data)

SoC

P2.2

P2.1

RESETn

Vdd

GND

Vdd

CC Debugger

Connector

CCxxxx

System-on-Chip

NOTE 2

Vdd

NOTE 1

10 kΩ

2.7 kΩ

1 nF

3.3 V from debugger.

Can optionally be

used to power the

target board

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Connecting the CC Debugger to the Device

Figure 6. Minimum Connection for Debugging of 8051 SoC

NOTE: Some early revisions of certain SoCs (CC2430, CC2510 and CC1110) needed an external

pull-up to avoid unwanted transitions on the debug clock line during chip reset, inadvertently

setting the device in debug mode. All new revisions of all SoCs now have an internal pull-up

on P2.2, so this external component is not required.

NOTE: The RESETn pin is sensitive to noise and can cause unintended reset of the chip. For reset

lines susceptible to noise, it is recommended to add an external RC filter. For recommended

RESET circuitry, see the device-specific SoC data sheet and reference designs. The CC

Debugger supports slow transitions on the reset line, using a 2 ms delay between any

transition on the RESET line and other transitions on the DC and DD lines.

6.2.2 Minimum Connection for SmartRF Studio

Use the same connection as for debugging the SoC.

SWRU197H–September 2010–Revised April 2014 CC Debugger

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