User`s guide
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GND
DC (Debug Clock)
RESETn
DD (Debug Data)
SoC
P2.2
P2.1
RESETn
Vdd
GND
Vdd
CC Debugger
Connector
CCxxxx
System-on-Chip
2.7 kΩ
1 nF
CSn
SCLK
MOSI
MISO
P1.7
P1.6
P1.5
P1.4
3.3 V from debugger.
Can optionally be
used to power the
target board
Connecting the CC Debugger to the Device
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6.2.3 Minimum Connection for SmartRF Packet Sniffer
In order to use the packet sniffer capabilities of the CC Debugger, it is also necessary to connect the SPI
bus to the SoC. The SPI interface is used by the CC Debugger for reading the captured RF packets from
the SoC (see Figure 7).
Figure 7. Connection to SoC to Enable Packet Sniffing
Note that the packet sniffer overwrites the Flash on the SoC with special packet capture firmware.
Note concerning the SPI interface to the SoC used for packet sniffing
All of the current TI RF SoCs can be configured to operate as SPI slaves, with the SPI signals (CS, SCLK,
MISO and MOSI) going to one of the USART peripherals. The packet sniffer application programs the
SoC with firmware that configures one of the USART peripherals in order to communicate with the CC
Debugger. The firmware can use any of the four possible pin configurations (USART 0 or 1, pin out
alternative 1 or 2). However, only a subset is currently supported (see Table 1).
Table 1. Supported SPI Connections (marked OK)
USART0, alt 1 USART0, alt 2 USART1, alt 1 USART1, alt 2
CC243x - - - OK
CC253x/CC254x - - - OK
CC111x OK - - OK
CC251x OK - - OK
Table 2. USART Pin Out Details
USART0, alt 1 USART1, alt 2
SCLK P0.5 P1.5
CS P0.4 P1.4
MOSI P0.3 P1.6
MISO P0.2 P1.7
In case of multiple supported interfaces, the Packet Sniffer application lets you choose which interface to
use.
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CC Debugger SWRU197H–September 2010–Revised April 2014
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