User's Manual

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14
3.9 Inter-integrated circuit interface (I2C)
Up to three I2C bus interfaces can operate in master or slave modes. They can support standard (up
to 100 kHz) and fast (up to 400 kHz) modes. The I2C bus frequency can be increased up to 1 MHz.
They also support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A
hardware CRC generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
The ALXC2X also include programmable analog and digital noise filters
Table 2 Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
>= 50ns
Programmable length from 1 to 15 I2C peripheral clock
3.1 0 Analog-to-digital converter (ADC)
One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels,
performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is
performed on a selected group of analog inputs.
The ADC can be served by the DMA controller. An analog watchdog feature allows very precise
monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated
when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3,
or TIM4 timer.
3.1 1 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or
without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as
peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate
functions. All GPIOs are high-current-capable and have speed selection to better manage internal
noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to avoid
spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 100 MHz
3.1 2 JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that
enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed
using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate
function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific
sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.