User's Manual

ALXC2X DATASHEET
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communication modes. The SPI can communicate at up to 50Mbit/s. The 3-bit pre-scaler gives 8
master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by DMA
controller.
The SPI interface can be configured to operate in TI mode for communications either in master mode
or slave mode.
3.7 Universal series bus (USB)
The ALXC2X embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers.
The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0
specification. It has software-configurable endpoint setting and supports suspend/resume. The USB
OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected
to the HSE oscillator. The major features are:
 Combined RX and TX FIFO size of 320 × 35 bits with dynamic FIFO sizing
 Supports the session request protocol (SRP) and host negotiation protocol (HNP)
 4 bidirectional endpoints
 8 host channels with periodic OUT support
 HNP/SNP/IP inside (no need for any external resistor)
 For OTG/Host modes, a power switch is needed in case bus-powered devices are connected
3.8 Inter-integrated Sound (I2S)
Five standard I2S interfaces (multiplexed with SPI1 to SPI5) are available. They can be operated in
master or slave mode, in simplex communication modes or full duplex for I2S2 and I2S3, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. All the I2Sx audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S
interfaces are configured in master mode, the master clock can be output to the external
DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
The ALXC2X features an additional dedicated PLL for audio I2S applications. It allows error-free I2S
sampling clock accuracy without compromising on the CPU performance.
The PLL I2S configuration can be modified to manage an I2S sample rate change without disabling
the main PLL used for the CPU.
The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 kHz
to 192 kHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with
an external PLL (or Codec output).