Specifications
Rev. 1.0 January 2012
www.aosmd.com
Page 13 of 13
AOZ197
8
For typical application, we recommend to set the
voltage at CS to approximately 0.3V when inductor
current reaches the peak. To accommodate load, line
and inductor tolerances variation, 30% margin is
included in the above calculation.
R
RTN
Ground return current sense resistor, this
resistor is optional and if desired can be used to add
an extra layer of protection against output shorts or
any other fault condition that causes excessive return
current.
When not used, simply connect a 1V divider from
PVIN to SCP pin. In this configuration SCP pin will
function as a typical under-voltage lock out (UVLO)
pin with a rising threshold of 1V and a falling threshold
of 0.8V.
If short circuit protection is desired then:
V
I
R
AVGIN
RTN
2.0
PVIN
VLEDILEDVLEDILED
I
AVGIN
2211
When R
RTN
is used then the divider from PVIN to SCP
pin will have to be calculated as a 1.34V divider to
compensate for the 0.2V drop generated by R
RTN
, and
also this divider will now be referenced to RTN
Ground. A small cap is required from SCP pin to IC
Ground to integrate the sensed voltage and avoid
premature protection (see typical application circuit).
Boost Feedback Loop Compensation
The AOZ1978 employs peak current mode control for
easy use and fast transient response. Peak current
mode control eliminates the double pole effect of the
output L&C filter. It greatly simplifies the
compensation loop design.
With peak current mode control, the boost power
stage can be simplified to be a one-pole, one left
plane zero and one right half plane (RHP) system in
frequency domain. The pole is dominant pole and can
be calculated by:
LO
P
RC
f
2
1
1
The zero is a ESR zero due to output capacitor and its
ESR can be calculated by:
COO
Z
ESRC
f
2
1
1
where,
C
O
is the output filter capacitor,
R
L
is load resistor value, and
ESR
CO
is the equivalent series resistance of output
capacitor.
The RHP zero has the effect of a zero in the gain
causing an imposed +20dB/decade on the roll off, but
has the effect of a pole in the phase, subtracting 90
in
the phase. The RHP zero can be calculated by:
OO
IN
Z
VIL
V
f
2
2
2
The RHP zero obviously can cause instability issue if
the bandwidth is higher. It is recommended to design
the bandwidth to lower than the one half frequency of
RHP zero.
The compensation design is actually to shape the
converter close loop transfer function to get desired
gain and phase. Several different types of
compensation networks can be used for AOZ1978.
For most cases, a series capacitor and resistor
network connected to the COMP pin sets the pole-
zero and is adequate for a stable high-bandwidth
control loop.
In the AOZ1978, FB pin and COMP pin are the
inverting input and the output of internal
transconductance error amplifier. A series of R and C
compensation network connected to COMP provides
one pole and one zero. The pole is:
VEAC
EA
P
GC
G
f
2
2
where,
G
EA
is the error amplifier transconductance, which is
200·10
-6
A/V,
G
VEA
is the error amplifier voltage gain, which is 1000
V/V, and
C
C
is compensation capacitor.
The zero given by the external compensation network,
capacitor C
C
and resistor R
C
, is located at:
CC
Z
RC
f
2
1
2
Choose the suitable C
C
and R
C
by trading-off stability
and bandwidth.