Instructions

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6.2.1.3 Rising edge (RTRIG)
Fig. 6.41
Detector for a rising edge
The output Q remains False until a rising edge at the input I. As soon as the input I be-
comes True, the output becomes also True and remains for one program cycle.
Fig. 6.42
6.2.1.4 Falling edge (FTRIG)
Fig. 6.43
Detector for a falling edge
The output Q remains False until a falling edge at the input I. As soon as the input I be-
comes False, the output becomes True and remains for one program cycle.
Fig. 6.44
6.2.1.5 D-trigger (DTRIG)
Fig. 6.45
D-trigger generates a pulse at the output Q with the pulse duration specified at the input
D and synchronized with the clock pulse at the input С.
If the input D is True, the output Q becomes True with a rising edge of the clock pulse at
the input C.
If the input D is False, the output Q becomes False with a rising edge of the clock pulse
at the input С.