User`s guide

Aironet Wireless Communications, Inc. 7-8 Confidential and Proprietary

Command and Status Register Descriptions

The PC4500/4800 provides 4 I/O registers for issuing commands to the protocol processor and 4 I/O

registers for status response. These registers provide a command / status interface for sequential protocol

processor control functions. The command code and related information is entered in the Command and

Param registers. The process is executed by the PC4500/4800 and then the resulting status is provided in

the Status and Resp registers. Completion of a command is signaled and acknowledged using the Event

registers.

The command response mechanism provides semaphores on the command/response to prevent the host

from overwriting a command that has not yet been processed and to prevent the PC4500/4800 from

overwriting a response. The mechanism allows the host to issue a new command after the PC4500/4800

has acknowledged, but is still processing the previous command. Note, a command may be stalled in the

Command/Param registers until a previous response is acknowledged.

The sequence for issuing a command to the PC4500/4800 is as follows:

1. wait for Command.Busy to be clear

2. write the required parameters (Param0, Param1, Param2)

3. write the command (Command)

4. wait for EvStat.Cmd to indicate that the command has completed

5. read the completion status and responses (Status, Resp0/1/2)

6. acknowledge the command by setting EvAck.Cmd

When the command completes, the Status register will contain the command code in the lower byte. If

the command completed successfully, the upper byte of the Status will be zero, and Resp0, Resp1 and

Resp2 will contain responses that change depending on the command.

If the command failed, the upper byte of the Status Register will be non-zero, and Resp0 will contain the

error code. Additional information may be conveyed in Resp1 and Resp2 depending on the command.

Some commands allow for successful completion to not be indicated to the host. This is accomplished

by setting the NoResponse bit when writing the Command Register. If the command successfully

executes, there will be no EvStat.Cmd event. If the command fails, a response will be returned as

normal.

If commands are to be issued from multiple contexts (e.g. interrupt routines) then interrupts should be

disabled as appropriate to prevent a context switch from causing improper operation:

1. wait for Command.Busy to be clear

2. disable interrupts;

3. if Command.Busy is set, reenable interrupts and return to step 1

4. write the required parameters (Param0, Param1, Param2)

5. write the command (Command)

6. reenable interrupts;

7. .... as above ...

A command will stall in the command register (Command.Busy won’t clear) if a previous command

completion (EvStat.Cmd is set) has not been acknowledged. Setting EvAck.Cmd will acknowledge the

previously unacknowledged command and allow the firmware to proceed with the new command.

In some circumstances, a command may be issued that is not processed by the PC4500/4800. The

PC4500/4800 will always zero the Command register after accepting the command. If the Command

be reissued by writing the Command register again.