User`s guide

Aironet Wireless Communications, Inc. 7-2 Confidential and Proprietary

Host Attribute Memory

The host attribute memory consists of the CIS and the attribute memory registers. The complete

PC4500/4800 CIS description can be found in Appendix B.

The CIS is copied from the flash to the RAM during power on reset. (The READY signal remains

deasserted until the copy process is completed.)

Table 7.1 – Card Configuration Information

Offset Description

000H-300H Card Information Structure (CIS)

3E0H Configuration Option Register must set to 0x45 to enable Host

control (I/O) Registers.

3E2H Card Configuration and Status Register

3E4H Pin Replacement Register

3E6H Socket and Copy Register (not used)

Host Common Memory

There is no common memory accessible on the PC4500/4800.

Host I/O Registers

The host has 32 consecutive 16-bit I/O registers for accessing the PC4500/4800 card. Table 7-2 lists the

All registers (except for the Data0, Data1 and AuxData) can be read without restriction since the read

operation will not impact the PC4500/4800 protocol processor. The exceptions require that an internal

data pointer be affected.

All registers are 16-bit registers, therefore, it is assumed that the host software writes or reads 16 bits per

I/O cycle. If the hardware environment is only capable of transferring 8 bits per I/O cycle, the register

word should be transferred as follows: first the low-order byte (bits 0-7) should be accessed via the I/O

undefined processor behavior, both bytes must be transferred before any other access is allowed

(includes another register access as well as an attribute memory access).