User`s guide

Aironet Wireless Communications, Inc. 5-4 Confidential and Proprietary
51 VCC VCC
52 VPP2 GND Sets ISA mode; enabling interface
53 A22 N/C
54 A23 N/C
55 A24 N/C
56 A25 N/C
57 VS2 N/C
58 RESET RESET Active high
59 WAIT# IOCHRDY Active low (See Note 3)
60 INPACK N/C (See Note 5)
61 REG# REG# Must be driven low according to PCMCIA spec
62 SPKR N/C
63 STSCHG STSCHG Open collector output signal
64 D8 D8
65 D9 D9
66 D10 D10
67 CD2 N/C
68 GND GND
Notes:
1
N/C indicates not connected.
2
The PC4500/4800 fully supports 8 bit I/O as well as 16-bit I/O. Since IOIS16# is tied to ground, it is not
shown on the timing diagrams.
3
Support of the WAIT# signal is required. Typical pulse widths for this signal are 250 to 500 nsec, but
can be as long as 875 nsec. Accesses to hardware base registers will have a WAIT# pulse width of
approximately 125nsec.
4
Both memory writes and I/O writes require a minimum valid data setup time of 15nsec ahead of the
rising edge of MEMW# or IOWR#.
5
The INPACK signal is returned for all I/O accesses. The use of this signal is not required since the
address is fully decoded by the socket controller.