User`s guide

Aironet Wireless Communications, Inc. 2-3 Confidential and Proprietary
The RF protocol processor is responsible for the low-level protocol functions including the formation of
the packet headers, data scrambling and descrambling, error checking, and packet acknowledgment as
well as the accomplishment of the higher-level MAC functions and RF network management functions.
The 256KB (128Kx16) of SRAM is used for shared memory between the host processor and the
PC4500/4800, buffer storage by the MAC processor, as well as stack, variable, and buffer space required
by the MAC processor.
The 256KB of Flash memory can only be accessed by the MAC processor, and is used for program and
radio calibration data storage.
The PC4500/4800 card has a serial prom containing a unique MAC ID for each card. This address can
be overridden for applications requiring manually configured MAC addresses.
The PC4500/4800 supports three types of host interfaces: a standard PCMCIA interface, an ISA mode
interface, or a UART style serial port.
The PC4500/4800 PCMCIA interface is compliant to the PCMCIA PC Card standard 3.0 electrical and
physical specifications and dynamically responds to 16 bit and 8 bit accesses. This interface provides
access to attribute memory (CIS configuration data) and I/O port (host registers). Access to the MAC
controller registers and shared memory is via I/O addresses, which requires minimum resources from a
host processor. Attribute memory is standardized to even-byte accesses. See Chapter 7 for a description
of the host interface registers.
PC4500/4800 Software Overview
The PC4500/4800 implements a sophisticated wireless data protocol with a direct sequence spread-
spectrum physical layer. This protocol is handled transparently to the user. The data delivery interface is
accomplished through a command interface and transmit and receive data buffers.
PCMCIA and ISA operation requires a region of I/O space and an available interrupt. All data transfers
to the PC4500/4800 use I/O reads and writes. Serial operation of the PC4500/4800 requires standard PC
serial port drivers.
A section of memory is available which is arbitrated among the host process and the MAC processes
running on the PC4500/4800. This memory contains the required command and status areas, transmit
and receive buffers, and statistics and configuration information. These memory regions are mapped into
the host’s I/O space (usually via card and socket services) through 32 contiguous 16-bit I/O registers.
PC4500/4800 Protocol Overview
The PC4500/4800 implements a sophisticated wireless data protocol with a direct sequence spread-
spectrum physical layer. For detailed information on the protocol, consult the IEEE 802.11 Wireless
LAN specification. Chapter 3 contains an overview of the 802.11 protocol and highlights some
extensions to the protocol provided by Aironet Wireless Communications.
The RF protocol used on the PC4500/4800 is a CSMA/CA (Carrier Sense Multiple Access with Collision
Avoidance) system. This protocol provides a best effort packet delivery service with guaranteed data
integrity by using extensive error checking (16-bit and 32-bit CRCs), length checks, sequence fields,
packet flow control, and low-level packet acknowledgments. Once a directed packet is received by the
PC4500/4800, an acknowledge is immediately sent informing the source that the packet was received
correctly. If a packet is lost due to either a CRC error or a collision in the air with another packet, the
sending station will not get an acknowledgment and the packet will automatically be retransmitted.