User`s guide

Aironet Wireless Communications, Inc. 2-1 Confidential and Proprietary
2
CHAPTER 2 A
PC4500/4800 Architecture
This chapter presents the high level design details of the PC4500/4800 and describes some of the features
available from the hardware and software.
System Overview
The PC4500/4800 can be referred to as an RF modem and is responsible for handling the lowest two
layers (Physical and Data Link) of the OSI protocol reference model. These layers are also referred to as
the PHY (Physical) and MAC (Data Link) layers. The PHY layer is responsible for formatting the data
into a form suitable for delivery as a radio signal. The MAC (media access control) layer is responsible
for formatting the data and timing the delivery of the actual data packet.
Within the MAC layer, functions are divided into two levels. The lower level will handle the data
delivery aspects of the wireless network including packet formatting and RF acknowledgment. The
higher level is responsible for wireless network management. Some of the lower level functions are
performed by hardware but most functionality is determined by software routines executing on a
microcontroller protocol processor.
Executing on the host will typically be NDIS, ODI, or packet drivers which encompass the third and
fourth layers of the OSI model (Network and Transport layers). These device drivers communicate to the
protocol processor via an IO interface and/or interrupts.
PC4500/4800 Hardware Overview
The PC4500/4800 is a direct sequence spread-spectrum wireless network adapter. It uses a standard PC
card interface, ISA interface, or a UART style serial interface to communicate to a host process. The
main components of the PC4500/4800 architecture are: RF protocol processor, SRAM, Flash ROM, host
interface, and direct sequence radio.