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TM PC4500/PC4800 PC Card Wireless LAN Adapter Developer’s Reference Manual
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of Aironet Wireless Communications. Information in this document is subject to change without notice. Aironet Wireless Communications makes no representations or warranties with respect to the contents or use of this manual and specifically disclaims any express or implied warranties of merchantability or fitness for any particular purpose.
Contents PART 1 INTRODUCTION About the Developer’s Reference Manual ……………………………………... Typographical Conventions ……………………………………………………….. Reference Documents …………………………………………………………… Welcome to the PC4500/4800 …………………………………………………… System Configurations ………………………………………………………………... Coverage Options ……………………………………………………………………. vii ix x 1-1 1-2 1-2 PART 2 GETTING STARTED Hardware Architecture …………………………………………………………. System Overview ……………………………………………………………………. Hardware Overview …………………………………………………………………..
Resetting the PC4500/4800 ……………………………………………………………. Interrupt Service Routine (ISR) processing ……………………………………………… Enabling the PC4500/4800 …………...……………………………………………….. Command and Status Register Descriptions ……………………………………………… Command Register ……………………………………………………………... Param0-2 Registers ………………..……………………………………………. Status Register …………………………..……………………………………... Resp0-2 Registers ……………………………………………………………… Event Register Descriptions …………………………………………………………. EvStat Register ………………………………………………………………...
Frame Info Descriptor ……………………………………………………………… FID with 802.3 Header – Station Mode …………………………………………… Receiving an 802.3 Packet ……………………………………….…………... Transmitting an 802.3 Packet ………………………………………………... FID without 802.3 Header – Access Point Mode …………………………………… Receiving an 802.11 Packet …………………………………………………. Transmitting an 802.11 Packet ……………………………………………….. FID Field Details ……………………………………………………………….. Resource Identifiers ………………………………………………………………... General Configuration Parameters …………………………………………………….
CONFIGURE ……………………………………………………………………. DOWNLOAD …………...………………………………………………………. HOST_COMMAND ……………………………………………………………. COMMAND_RESPONSE ……………………………………………………… PLAP Boot Strap of PC4500/4800 ………………………………………………... PART 5 REFERENCE OEM Radio Approval Information …………………………………..……….. Safety Approvals ………………………………………………………….………… FCC Approvals ……………………………………………………….……………. DOC Approvals (Canada) ……………………………………………………………. ETSI Approvals (Europe) ……………………………………………………………. OEM Labeling Requirements ………………………………………………………….
List of Figures Figure 1.1 Figure 1.2 Figure 1.3 Figure 2.1 Figure 2.2 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 8.1 - Minimal Overlap Coverage Option ………………………………………………… Heavy Overlap Coverage Option …………………………………………………… Multiple Overlapping Systems Coverage Option …………………………………... Protocol Model ……………………………………………………………………... Hardware Block Diagram …………………………………………………………... Architecture Reference Model ……………………………………………………...
List of Tables Table A.1 Table A.2 Table A.3 Table A.4 Table B.1 - Green LED Operating Messages …………………………………………………… Amber LED Operating Messages ………………………………………………….. LED Error Codes …………………………………………………………………... Power Requirements ………………………………………………………………… CIS Information ……………………………………………………………………. Aironet Wireless Communications, Inc.
PREFACE A About the Developer’s Reference Manual This guide provides detailed information to aid a developer with both hardware and software interfacing to the PC4500 and PC4800. Please consult the User’s Guide & Technical Reference Manual, PC4500/4800 (DOC 710-004239) which covers installation and maintenance as well configuration with standard operating systems and network drivers before attempting to install or use the hardware and software described in this guide.
Chapter 4 - PCMCIA Interface - contains information necessary when designing a PCMCIA host interface to the PC4500/4800. Chapter 5 - ISA Interface - contains information necessary when designing an ISA host interface to the PC4500/4800. Chapter 6 - Serial Interface - contains information necessary when designing a serial host interface to the PC4500/4800.
Typographical Conventions When reading the Developer’s Reference Manual, it is important to understand the symbol and formatting conventions used in the documentation. The following kinds of symbols and formatting are used in the guide. Convention I Type of Information Indicates a note which contains important information set off from the normal text. ! A caution message that appears before procedures which if not observed could result in loss of data or damage to the equipment.
Reference Documents Aironet Documents: “Aironet Antenna Guide” (document number 710-003725) “User’s Guide and Technical Reference Manual, PC4500/4800” (document number 710-004239) “User’s Guide, AP4500/4800-E/T” Ethernet and Token Ring versions (document number 710-004240) “Technical Reference Manual, AP4500/4800-E/T” Ethernet and Token Ring versions (document number 710-004242) Third Party Documents: IEEE Standard 802.
1 INTRODUCTION A Welcome to the PC4500/4800 The PC4500 and the PC4800 are radio modules (typically used to create indoor wireless networks and limited distance outdoor applications) that provide transparent wireless data communications between a fixed, portable or mobile device and other wireless devices (such as access points connected to a wired network infrastructure). Host devices can be any device equipped with a PC Card Type II or Type III slot mechanical form factor.
standard. The PC4500/4800 WEP is capable of using 128 bit keys for additional security above the 802.11 standard which specifies the use of 40 bit keys. System Configurations The PC4500/4800 can be used in a variety of network system configurations. Aironet access points can be used to provide a wireless connection to an ethernet or token ring wired network.
Figure 1.1 - Minimal Overlap Coverage Option By arranging AP4500/4800 access points such that the overlap in coverage area is minimized, a large area can be covered with minimal system cost. The total bandwidth available to each mobile client will depend upon the amount of data each mobile client desires to transfer and the number of clients located in each cell as well as the data rates used for transmission.
By arranging AP4500/4800 access points such that the overlap in coverage area is nearly maximized, a large number of mobile clients can be supported in the same general coverage area without any degradation in system performance or connect time. In addition, due to the redundancy in coverage overlap, system performance is not hampered in the event of an access point failure because clients will automatically ‘roam’ to an operational access point.
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2 CHAPTER 2 A PC4500/4800 Architecture This chapter presents the high level design details of the PC4500/4800 and describes some of the features available from the hardware and software. System Overview The PC4500/4800 can be referred to as an RF modem and is responsible for handling the lowest two layers (Physical and Data Link) of the OSI protocol reference model. These layers are also referred to as the PHY (Physical) and MAC (Data Link) layers.
APPLICATION Application Programs PRESENTATION Network Operating Systems SESSION NOS Software Interface TRANSPORT Network Driver NETWORK Aironet LAN Cards Aironet Programmer’s Interface DATA LINK PHYSICAL Figure 2.1 - Protocol Model 128K x 16 SRAM SA[16:0] PCMCIA ISA UART Host Interface SD[15:0] SCTRL HD[15:0] HA[9:0] RXD MAC Protocol Processor TXD 2.4 GHz DS Radio HCTRL RCTRL FD[7:0] FA[17:0] 256K x 8 Flash ROM Figure 2.
The RF protocol processor is responsible for the low-level protocol functions including the formation of the packet headers, data scrambling and descrambling, error checking, and packet acknowledgment as well as the accomplishment of the higher-level MAC functions and RF network management functions.
Upon successful reception of a complete packet, the PC4500/4800 will inform the host processor that it has a packet in its buffer. Duplicate packets are filtered out via the use of frame sequence numbers in the header of each frame. The implemented RF protocol and media access techniques used by the PC4500/4800 cannot be altered by the programmer. Variations are limited primarily to setting the operating channel(s), maximum packet size, packet fragmentation size, flow control, and number of packet retries.
3 CHAPTER 3 A Overview of the 802.11 Wireless LAN Protocol The IEEE 802.11 Wireless LAN Specification addresses only the lowest two layers of the protocol model. The main intent is to provide a framework such that multiple vendors can design interoperable products. When compared to a wired protocol (like 802.
The MAC entity provides the basic access mechanisms to the RF medium and is responsible for functions such as encryption and fragmentation. The MAC layer management is responsible for the synchronization functions, power management and roaming coordination. The PHY layer management is primarily responsible for channel tuning and coordination of the radio functions. The PLCP sublayer is responsible for clear channel assessment of the RF channel.
802.11 Direct Sequence Frame Format Figure 3.2 depicts the frame format used for each packet transmission. SYNC 128bits SFD 16 bits PLCP Preamble 144 bits SIGNAL 8 bits SERVICE 8 bits PLCP Header 48 bits LENGTH 16 bits CRC 16 bits MPDU PPDU Figure 3.2 - PHY Header Description Each frame consists of a PHY header which is always transmitted at the 1 Mbit/s data rate. The PHY header (which is protected by a CRC-16) indicates the data rate and length of the data portion of the payload.
specification. The format of each of the individual frame types is defined in section 7.2 of the IEEE 802.11 specification. Octets: 2 2 Frame Control Duration/ ID 6 6 6 Address 1 Address 2 Address 3 2 6 Sequence Address 4 Control 0 - 2312 4 Frame Body FCS MAC Header Figure 3.3 - MAC Control Information The 2 byte Frame Control field consists of the following sub-fields: Protocol Version, Type, Subtype, To DS, From DS, More Fragments, Retry, Power Management, More Data, WEP and Order.
Basic Station operation A Station keeps two state variables for each station with which direct communication via the wireless medium is needed: Authentication State: The values are: Unauthenticated and Authenticated. Association State: The values are: Unassociated and Associated. These two variables create three local states for each remote station: State 1: Initial start state, Unauthenticated, Unassociated. State 2: Authenticated, not Associated State 3: Authenticated and Associated.
Table 3.1 – 802.11 Frame Types Subtype Value b7 b6 b5 b4 MANAGEMENT frames (type 00) 0000 0001 0010 0011 0100 0101 0110-0111 1000 1001 1010 1011 1100 1101-1111 CONTROL frames (type 01) 0000-1001 1010 1011 1100 1101 1110 1111 DATA frames (type 10) 0000 0001 0010 0011 0100 0101 0110 0111 1000-1111 Reserved (type 11) 0000-1111 Aironet Wireless Communications, Inc.
State 1: Unauthenticated, Unassociated Class 1 Frames Successful Authentication DeAuthentication Notification DeAuthentication Notification State 2: Authenticated, Unassociated Class 1 & 2 Frames Successful Association or Reassociation Class 1, 2 & 3 Frames Disassocaiation Notification State 3: Authenticated and Associated Figure 3.4 - Relationship Between State Variables and Services The current state existing between the source and destination station determines the 802.
Class 2 frames (if and only if authenticated; allowed from within state 2 and state 3 only): Management frames: • Association Request/Response Successful association enables Class 3 frames. Unsuccessful association leaves station in state 2. • Reassociation Request/Response Successful reassociation enables Class 3 frames. Unsuccessful reassociation leaves the station in State 2 (with respect to the station which was sent the reassociation message).
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4 CHAPTER 4 A PCMCIA Hardware Interface Operation This chapter details the hardware aspects of the PC4500/4800 PCMCIA host interface. See Chapter 7 for details about the PCMCIA software interface. PCMCIA Hardware The PC4500/4800 PCMCIA interface is compliant to the PCMCIA PC Card standard electrical and physical specifications and fully supports 8 and 16 bit transfers. The tables below summarize the interface signals. For complete descriptions, see the PCMCIA PC Card standard.
PCMCIA Electrical Connections PIN # 1 34 35 68 17 51 18 52 PC4500/4800 Power Connections I/O NAME FUNCTION DC GND Ground DC GND Ground DC GND Ground DC GND Ground DC VCC 5V supply voltage DC VCC 5V supply voltage DC VPP1 Programming supply voltage, Host mode selection switch DC VPP2 Programming supply voltage, Host mode selection switch Notes: VPP – both VPP lines should be set to 5V on start up in order to indicate PCMCIA host mode.
PC4500/4800 Data Connections PIN # 41 40 39 38 37 66 65 64 6 5 4 3 2 32 31 30 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Data bit 15 Data bit 14 Data bit 13 Data bit 12 Data bit 11 Data bit 10 Data bit 9 Data bit 8 Data bit 7 Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 Notes: D[15:0] - Bidirectional data bus signals for even-byte access to the attribute memory as well as byteonly
Notes: CE1#, CE2#, IORD#, IOWR#, OE#, REG#, WAIT#, WE# - Input signals for bus control as defined in the PCMCIA standard. INPACK#, IOIS16#, STSCHG# - Output signals for bus control as defined in the PCMCIA standard. RESET - Input signal for resetting the PC4500/4800. This signal must be asserted for a minimum of 20 microseconds. IREQ# - Output signal that functions as the RDY/BSY line following the deassertion of the RESET signal until the PC4500/4800 is configured and ready for operation.
PIN # 43 57 62 8 10 21 13 14 20 19 46 47 48 49 50 53 54 55 56 PC4500/4800 Unused Connections I/O NAME FUNCTION O VS#1 O VS#2 O SPKR# This pin is pulled high on the PC4500/4800 I A10 I A11 I A12 I A13 I A14 I A15 I A16 I A17 I A18 I A19 I A20 This pin is used as DTR for Serial mode operation I A21 This pin is used as RTS for Serial mode operation I A22 This pin is used as CTS for Serial mode operation I A23 This pin is used as DCD for Serial mode operation I A24 This pin is used as RXD for Serial mode opera
5 CHAPTER 5 A ISA Hardware Interface Operation This chapter details the hardware aspects of the PC4500/4800 ISA host interface. See Chapter 7 for details about the ISA software interface. ISA Hardware The PC4500/4800 ISA interface functions as either an 8-bit (byte only) or a 16-bit (word only) I/O interface device. The interface does not adhere to all signal definitions according to the ISA specification as some signals must be driven according to the PCMCIA specification.
Configuration Options register (COR) does not need to be written to access the card. All other interface registers act the same. All signals and timings are the same as in PCMCIA mode except that the sense of the interrupt line becomes active high in ISA mode. In ISA mode, the PC4500/4800 requires external hardware to determine the IRQ and I/O base address that the card uses.
PCMCIA definition GND D3 D4 D5 D6 D7 CE1# ISA definition GND D3 D4 D5 D6 D7 CE1# 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 A10 OE# A11 A9 A8 A13 A14 WE# IREQ# VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16# GND GND CD1# D11 D12 D13 D14 D15 CE2# N/C MEMR N/C A9 A8 N/C N/C MEMW INT0 VCC VCC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOCS16# GND GND N/C D11 D12 D13 D14 D15 CE2# 43 44 45 VS1 IORD# IOWR# N/C IOR# IOW# 46 47 48 4
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 VCC VPP2 A22 A23 A24 A25 VS2 RESET WAIT# INPACK REG# SPKR STSCHG D8 D9 D10 CD2 GND VCC GND N/C N/C N/C N/C N/C RESET IOCHRDY N/C REG# N/C STSCHG D8 D9 D10 N/C GND Sets ISA mode; enabling interface Active high Active low (See Note 3) (See Note 5) Must be driven low according to PCMCIA spec Open collector output signal Notes: 1 N/C indicates not connected. 2 The PC4500/4800 fully supports 8 bit I/O as well as 16-bit I/O.
I/O Read Cycle tsu AD[7:0] IORD# th A[7:0] (IORD#) PCMCIA_A[9:0] tsu REG# (IORD#) th REG# (IORD#) tsu CE# (IORD#) th CE# (IORD#) PCMCIA_REG# PCMCIA_CE1#, PCMCIA_CE2# tw IORD# td INPACK# IORD# td WAIT# (IORD#) td INPACK# IORD# th D[15:0] (IORD#) PCMCIA_IORD# PCMCIA _INPACK# tw (WAIT#) tdr D[15:0] (WAIT#) PCMCIA_WAIT# thd D[15:0] (IORD#) PCMCIA_D[15:0] NAME tw (WAIT#) tw (IORD#) tsu REG# (IORD#) tsu CE# (IORD#) tsu A[7:0] (IORD#) td INPACK# (IORD#) td WAIT# (IORD#) th A[7:0] (IORD#) th REG# (IORD#)
I/O Write Timing tsu AD[7:0] IOWR# th A[7:0] (IOWR#) tsu REG# (IOWR#) th REG# (IOWR#) PCMCIA_A[8:0] PCMCIA_REG# tsu CE# (IOWR#) th CE# (IOWR#) PCMCIA_CE1#, PCMCIA_CE2# tw IOWR# td WAIT# (IOWR#) td INPACK# IOWR# tsu D[15:0] IOWR# td INPACK# IOWR# th D[15:0] (IOWR#) PCMCIA_IOWR# PCMCIA _INPACK# tw (WAIT#) td IOWR# (WAIT#) PCMCIA_WAIT# thd D[15:0] (IOWR#) PCMCIA_D[15:0] NAME tw (WAIT#) tw (IOWR#) tsu REG# (IOWR#) tsu CE# (IOWR#) tsu A[7:0] (IOWR#) td INPACK# (IOWR#) td WAIT# (IOWR#) th A[7:0] (IOWR
Attribute Memory Read Timing 3 1 tsu AD[7:0] (OE#) th A[9:0] (OE#) tsu REG# (OE#) th REG# (OE#) PCMCIA_A[9:0] PCMCIA_REG# tsu CE# (OE#) th CE# (OE#) PCMCIA_CE1#, PCMCIA_CE2# tw OE# td WAIT# (OE#) tsu D[15:0] OE# th D[15:0] (OE#) PCMCIA_OE# tw (WAIT#) td OE# (WAIT#) PCMCIA_WAIT# thd D[15:0] (OE#) PCMCIA_D[15:0] NAME tw (WAIT#) tw (OE#) tsu REG# (OE#) tsu CE# (OE#) tsu A[7:0] (OE#) td WAIT# (OE#) th A[9:0] (OE#) th REG# (OE#) th CE# (OE#) th D[15:0] (OE#) thd D[15:0] (OE#) td OE# (WAIT#) tsu D[15:
Attribute Memory Write Timing tsu AD[7:0] WE# th A[7:0] (WE#) tsu REG# (WE#) th REG# (WE#) PCMCIA_A[8:0] PCMCIA_REG# tsu CE# (WE#) th CE# (WE#) PCMCIA_CE1#, PCMCIA_CE2# tw WE# tsu D[15:0] WE# td WAIT# (WE#) th D[15:0] (WE#) PCMCIA_WE# tw (WAIT#) td IOWR# (WAIT#) PCMCIA_WAIT# thd D[15:0] (WE#) PCMCIA_D[15:0] NAME tw (WAIT#) tw (WE#) tsu REG# (WE#) tsu CE# (WE#) tsu A[7:0] (WE#) td WAIT# (WE#) th A[7:0] (WE#) th REG# (WE#) th CE# (WE#) th D[15:0] (WE#) thd D[15:0] (WE#) td IOWR# (WAIT#) tsu D[15:0]
6 CHAPTER 6 A Serial Hardware Interface Operation This chapter details the hardware aspects of the PC4500/4800 Serial host interface. See chapter 8 for details about the available software interfaces. Serial Hardware The PC4500/4800 PC card offers a Serial Interface mode to the host device by re-mapping the upper PCMCIA address lines to a UART-type serial interface. This allows the PC4500/4800 to be embedded and interfaced to via a serial port.
Serial Port Mode Specifications SPECIFICATION 7200 bit/s to 115.2 kbit/s using no parity, 8 data bits, 2 stop bits Voltage Levels TTL levels supported ViL < 0.8V VoL < 0.3V ViH > 2.0V VoH > 3.0V ITEM Baud Rates Signal Polarity RXD, TXD (NRZ data, non inverted) CTS, RTS (active low) DSR, RING (active low) BUSY_IN, BUSY_OUT (active high) When Serial mode is required, the PC Card connections should be as shown in Table 6-2.
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 GND CD#1 D11 D12 D13 D14 D15 CE2# VS1# IORD# IOWR# A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 VS2 RESET Grounded N/C Grounded Grounded Grounded Grounded Grounded Tied high N/C Tied high Tied high N/C RING DSR DTR/BO RTS# Apply VCC Grounded CTS# DCD/BI RXD TXD N/C RESET 59 60 61 62 63 WAIT# INPACK# REG# SPKR# STSCHG# N/C N/C Tied high N/C O.C.
The following page provides a schematic to be used for interfacing the PC4500/4800 using a serial interface. This is a general drawing intended to be used with several Aironet PCMCIA card devices. The address and data lines of the PCMCIA connector can be left unconnected or may be tied to ground for proper PC4500/4800 operation. The following table gives some part number cross references.
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7 CHAPTER 7 A PCMCIA and ISA Client Software Interface This chapter details the software interface to the PC4500/4800. Refer to chapters 4 and 5 for details about the PCMCIA and ISA hardware interfaces. The main software components in a PCMCIA environment are Card Services and Socket Services. The use of these services provides sufficient abstraction to allow the use of multiple PC cards through different PCMCIA interface hardware.
Host Attribute Memory The host attribute memory consists of the CIS and the attribute memory registers. The complete PC4500/4800 CIS description can be found in Appendix B. The CIS is copied from the flash to the RAM during power on reset. (The READY signal remains deasserted until the copy process is completed.) Offset 000H-300H 3E0H 3E2H 3E4H 3E6H Table 7.
The following is sample code for accessing the PC4500/4800 I/O registers: unsigned short #if IO_IS_16BIT Base4500IO; // I/O base address #define #define #else OUT4500(register, u16value) IN4500(register) outportw(Base4500IO+register, u16value) inportw(Base4500IO+register) #define #define OUT4500(register, u16value) IN4500(register) out4500_8bit(register, u16value) in4500_8bit(register) // I/O is 16-bit // I/O is 8-bit void out4500_8bit(unsigned short register, unsigned short u16value) { push_inte
Table 7.
Bootstrap -- Starting the PC4500/4800 The following is the correct start sequence from the host perspective. 1. 2. 3. 4. 5. 6. 7. 8. 9. Wait for Card Detect signals to go active. Enable power (VCC) to the socket. Also, set VPP1, VPP2 = 5V. Delay for power to stabilize (200 ms). Release PCMCIA reset. Delay at least 10us. Wait for Card Ready to go active. Read the CIS to identify card. Configure socket to have an I/O window with 32 consecutive 16-bit ports. Set Card Configuration Options Register to 0x45.
Interrupt Service Routine (ISR) processing The correct interrupt service routine processing is as follows: 1.Disable the interrupt source on the host (mask the PIC). 2.Prepare the host for another interrupt (EOI the PIC). 3.Determine the active interrupts: active_interrupts = IN4500(EVSTAT); Note: even masked interrupts will be active. 4.Process the active interrupts. (See Event Handling for details). 5.Acknowledge the interrupts and disable the interrupt: OUT4500(EVACK, active_interrupts); 6.
After bootstrapping, the following is sample code for configuring and enabling the MAC: tdsCommand tdsResponse PC4500_CONFIG Cmd; Rsp; cfg; typedef struct { unsigned short unsigned char } PC4500_SSID; SsidLen; Ssid[32]; struct MySsid { u16 PC4500_SSID }={ u16RidLen; aSSID[2]; 0, { 6, "MYSSID" } { 0, "" } // see following section for definition // see following section for definition // see following section for definition // PC4500 will ensure that the RidLen is unchanged // SSID length and value //
Command and Status Register Descriptions The PC4500/4800 provides 4 I/O registers for issuing commands to the protocol processor and 4 I/O registers for status response. These registers provide a command / status interface for sequential protocol processor control functions. The command code and related information is entered in the Command and Param registers. The process is executed by the PC4500/4800 and then the resulting status is provided in the Status and Resp registers.
In some circumstances Command.Busy also may not clear. This may occur when the host reads the Command register at the same time as the firmware attempts to clear the Command.Busy bit. A work-around is available for clearing a stuck Command.Busy, by setting EvAck.ClearCommandBusy. If the firmware is not processing a command, the Command.Busy bit will be cleared.
typedef struct { unsigned short unsigned short #define #define #define #define #define #define #define #define unsigned short #define #define #define #define #define #define #define u16Len; u16OperatingMode; unsigned short unsigned short unsigned char unsigned char unsigned short unsigned short unsigned short unsigned short unsigned short unsigned short unsigned short unsigned short MODE_STA_IBSS MODE_STA_ESS MODE_AP MODE_AP_RPTR MODE_ETHERNET_HOST MODE_LLC_HOST MODE_AIRONET_EXTEND MODE_AP_INTERFACE u16R
#define unsigned short DISABLE_REFRESH _reserved1a[1]; unsigned short #define #define #define unsigned short unsigned short unsigned short unsigned short unsigned short unsigned short u16PowerSaveMode; POWERSAVE_CAM POWERSAVE_PSP POWERSAVE_PSP_CAM u16SleepForDtims; u16ListenInterval; u16FastListenInterval; u16ListenDecay; u16FastListenDelay; _reserved2[2]; unsigned short unsigned short unsigned short unsigned short unsigned short unsigned short unsigned short u16BeaconPeriod; u16AtimDuration; u16HopPer
Command Register (I/O offset 0x00) Bit # Name 15 14 busy Additional Info 13 12 11 10 9 8 7 6 5 No Ack 0 Command Code 4 3 2 1 0 This register is used to write commands. Busy is automatically set to 1 when a value is written to this register (irrespective of the actual value written) and reset to 0 when the command is accepted. A command written while the Busy bit is set to 1 will be neglected. The commands are described in detail in later sections.
Note: Although a command (and parameters) may be written to the Command and Param registers when Command.Busy is 0, the command will not be processed by the PC4500/4800 until the previous command is acknowledged via EvAck.Cmd event. Status Register (I/O offset 0x08) Bit # Name 15 0 14 13 Result 12 11 10 9 8 7 0 6 0 5 4 3 Command Code 2 1 0 This register is used to read the status resulting from a command execution. Status availability is signaled by the EvStat.Cmd bit.
The event descriptions related to the register bits are: Event Associated Description Registers Awake None – PSP This bit is used only in power save mode. mode Awake event is issued in response to an EvAck.Awaken. To allow for maximal power saving, the host must inform the PC4500/4800 that the host will no longer access the PC4500/4800. To leave this mode, the host must issue an EvAck.Awaken and then wait for EvStat.Awake. After EvStat.Awake, the PC4500/4800 is normally accessible.
The EvAck.Awaken provides a mechanism to awaken the card when in PowerSave mode. When the card is in maximum sleep mode, most registers are unavailable. Two writes, back-to-back, are required to awaken the PC4500/4800 -- the first will awaken the hardware, the second will actually issue the EvAck.Awaken.
Basic FID Access Memory items consist of: FIDs - Frame Identifiers (transmit/receive packets or allocated memory) RIDs - Resource Identifiers (configuration items) FID/RID are accessed using three I/O registers: selector, offset, data. The first register is the selector register, which chooses the desired FID/RID. The second register is the offset register, which selects the position within the FID/RID. The third register is the data register which allows reads and writes to the FID/RID.
TxComplFID Register (I/O offset 0x24) Bit # Name 15 14 13 12 Completed Transmit FID 11 10 9 8 7 6 5 4 3 2 1 0 This register is used to read the FID of transmit frame structure buffers. This FID becomes available as a result of a completion (or failure) of an asynchronous transmission initiated by a Transmit command. Completed transmit FID availability is signaled by the EvStat.Tx or the EvStat.TxExc bits.
Data0-1 Registers (I/O offsets 0x36 or 0x38) Bit # Name 15 Data 14 13 12 11 10 9 8 7 6 5 4 3 2 1 This register is used to write or read buffer data. The specific buffer and buffer word initially accessed is determined by values previously written to the related Select and Offset registers. When a word is written to or read from this register, the internal data pointer is automatically incremented. Therefore, repeated Data register access addresses consecutive buffer words.
Sample C-code bap0_setup(u16 rid, u16 offset) { OUT4500(SELECT0, rid); OUT4500(OFFSET0, offset); while (1) { status = IN4500(OFFSET0); if (status & BAP_BUSY) { if (timeout) { push_interrupt_enable_state(); disable_interrupts(); OUT4500(SELECT0, rid); OUT4500(OFFSET0, offset); pop_interrupt_enable_state(); restart_timeout(); } continue; } if (status & BAP_ERR) { return ERROR; } if (status & BAP_DONE) { return SUCCESS; } // this example uses SELECT0/OFFSET0/DATA0 // suggested timeout of 500 usec minimum //
LinkStat Register (I/O offset 0x10) Bit # Name 15 Loss sync 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 2 EventCode 1 This register is used to read information that qualifies a Link event generation. Link events are generated by an asynchronous connection control process initiated by the Enable command. Link event information availability is signaled by the Link bit in the EvStat register.
Host Software Registers These registers are available for storage of host software values. The register values are not changed or interpreted by the PC4500/4800 controller. SwSupport0-3 Registers (I/O offsets 0x28 - 0x2E) Bit # Name 15 14 13 SW support value 12 11 10 9 8 7 6 5 4 3 2 1 0 Host Auxiliary Registers These registers are available for AP host support. (Refer to the section on AP specific information for more details.
Command Descriptions COMMAND SUMMARY Command Number 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0008 0x000A 0x000B 0x000C 0x0010 0x0021 0x0028 0x0030 0x003E 0x003F 0x0085 0x0108 Command NOP Enable Disable Force a Loss of Sync Firmware Restart (soft reset) Go to Sleep (must be issued as 0x0085) Magic Packet Read the configuration from nonvolatile storage Allocate Transmit Buffer Transmit Deallocate NOP (same as 0x0000) Access RID Allocate Buffer PSP nodes (AP only) Set PHY register Transmitter Test G
Enable Command The Enable command is used to start operation of the card after writing the configuration information. Enable Command Command (0x00) 0x0001 Param0 (0x02) 0x0000 Param1 (0x04) 0x0000 Param2 (0x06) 0x0000 0x0101 0x0000 0x0000 0x0000 0x0201 0x0000 0x0000 0x0000 Basic Enable This option enables both the MAC and receive operations Enable Only the MAC Allows the PC4500/4800 to associate to an AP, but no received packets will be passed to the host.
Disable Command The disable command is used to disable the operation of the card, typically to allow for a change of the configuration and subsequent reenable.
Soft Reset Command This is equivalent to resetting the card. Note, if this command completes successfully, it does not issue a command done. Soft Reset Command Command (0x00) 0x0004 Param0 (0x02) 0x0000 Param1 (0x04) 0x0000 Param2 (0x06) 0x0000 Restart (reboot) the card.
Magic Packet Command This command is used by a host to tell the PC4500/4800 to start scanning for magic packets. Magic Packet Command Command (0x00) 0x0006 Param0 (0x02) 0x0000 Param1 (0x04) 0x0000 Param2 (0x06) 0x0000 Enter Magic Packet search mode PSP Nodes Command This command is issued by an AP host to indicate to the card that PSP nodes are associated. If PSP nodes are associated, then broadcast and multicast traffic will be deferred until the DTIM.
Transmit Command Command (0x00) 0x000B Param0 (0x02) Transmit FID Param1 (0x04) 0x0000 Param2 (0x06) 0x0000 Basic Transmit Transmit Responses = Success Status (0x08) 0x000B Resp0 (0x0A) 0x0000 Resp1 (0x0C) Transmit FID Resp2 (0x0E) 0x0000 Description Successful transmit command. (Transmit may still fail however). The original Transmit FID value is returned to the host for matching purposes. However, the FID is under firmware control and cannot be reused by the host.
The first word of all RIDs is the total length of the RID (in bytes) including this length field. To read a RID To write a RID 1.Use the Read RID command with the RID in the first parameter. 2.Read the RID using the BAP registers 1.Use the Read RID command with the RID in the first parameter. This ensures that the firmware BAP register access is correct. 2.Read the RID using the BAP registers. 3.Modify the appropriate fields using the BAP registers. 4.Write the RID using the Write RID command.
Set PHY Register Command The Set PHY register command takes: Param0 = PHY register offset Param1 = ClearBits Param2 = SetBits The PHY register will only be modified if ClearBits or SetBits are non-zero: Phy = (Phy & (~ClearBits)) | SetBits; In any event, the resultant (or existing if not modified) PHY value is returned in Resp0. To read a PHY register, set ClearBits and SetBits to zero.
static u16 data2rid(u16 *pDat, u16 lenDat, int *pStat) { u16 rid; int status; if (pDat && lenDat) { rid = PC4500_allocbuf(lenDat); if (rid == 0) { *pStat = 1; return 0; } status = bap0_write(rid, 0, pDat, lenDat); if (status != 0) *pStat = status; return rid; } return 0; } // transmitter testing command int PC4500_txtest(u16 *pCmd, u16 lenCmd, u16 *pFreq, u16 lenFreq, u16 *pPatt, u16 lenPatt) { tds4500command cmd; tds4500response rsp; int status = 0; u16 ridCmd, ridFreq, ridPatt; ridCmd = 0; ridFreq = 0; ri
Error Qualifier Values ERROR QUALIFIER LIST Error Qualifier 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x0080 0x0081 0x0082 0x0083 0x0084 0x0085 0x0086 0x0087 0x0088 0x0089 0x008A 0x008B 0x008C 0x008D Description No Qualifier (For Disable, it means already disabled!) Illegal command. Illegal format. Usually means some unsupported bits are set in the Command. Invalid FID. Invalid RID. Too Large MAC is not disabled.
Memory (FID/RID) Access The PC4500/4800 provides two sets of 3 I/O registers for reading and writing receive and transmit packets and statistics and configuration information. It is suggested that one set be used in an interrupt context and the other in a non-interrupt context. These registers are collectively known as the "BAP" registers.
// -- PC4500 missed it, try again OUT4500(SELECT0, rid); OUT4500(OFFSET0, offset); } } // requires call to bap0_setup() first bap0_read(u16 *pu16Dst, int bytelen) { bytelen = (bytelen + 1) & (~1); // round up to even value while (bytelen > 0) { // each access to DATA0 will auto-increment to next word *pu16Dst++ = IN4500(DATA0); bytelen -= 2; } return SUCCESS; } // requires call to bap0_setup() first bap0_write(u16 *pu16Src, int bytelen) { bytelen = (bytelen + 1) & (~1); // round up to even value while (byte
Reading and Writing RIDs Reading and writing RIDs requires use of commands in addition to the BAP registers. Prior to reading or writing the RID, the Access RID command must be issued. Also after modifying a RID, the Access RID command must be used to commit the changes. static tds4500command cmd; static tds4500response rsp; /* for issuing commands */ /* response from commands */ int PC4500_accessrid(u16 rid, u16 accmd) { u16 status; memset(&cmd, 0, sizeof(cmd)); cmd.command = accmd; cmd.
if (bap0_setup(rid, 0) != SUCCESS) return ERROR; bap0_write(pBuf, len); // ---now commit the rid data return PC4500_accessrid(rid, 0x100|CMD_ACCESS); } Frame Info Descriptor A Frame Information Descriptor (FID) is used to pass transmit and receive packets to and from the PC4500/4800. FIDs are passed to the host in the RxFid, TxAllocFid and TxComplFid registers. The FID is then accessed (read/written) using the BAP registers. The BAP registers consist of a Selector, Offset, Data registers.
FID with 802.3 Header – Station Mode Station drivers will typically configure the PC4500/4800 to have 802.3 headers in the FID. This allows the driver to ignore the details of the 802.11 wireless network header and simply transfer ethernet or LLC packets. For receive, this mode allows the host driver to efficiently read the most common fields with only one BAP setup. Typically the driver only needs to read the 802.3 Header and payload.
The following table shows the fields in the receive and transmit FID with an 802.3 Header. Offset Receive FID Control Header +0x00 RxTime +0x02 +0x04 Status +0x06 PayloadLen +0x08 Rsv/Signal +0x0A Rate/Freq +0x0C RxAssocCnt/Rsv +0x0E +0x10 PLCP +0x12 PLCP… 802.11 Header +0x14 FrameControl +0x16 Duration +0x18 Address1 +0x1A +0x1C +0x1E Address2 +0x20 +0x22 +0x24 Address3 +0x26 +0x28 +0x2A SeqCtl +0x2C Address4 +0x2E +0x30 Protocol GAP +0x32 GapLen ---Gap[ ] 802.
Receiving an 802.3 Packet The following is sample code for receiving a packet: typedef struct { /* 802.3 packet header (802.
Transmitting an 802.3 Packet The following is sample code for transmitting a packet: typedef struct { /* transmit control header */ unsigned long SwSupport; /* for use by host drivers */ unsigned short Status; unsigned short PayloadLen; unsigned short TxControl; #define TXCTL_TXOK (1<<1) /* report if tx is ok */ #define TXCTL_TXEX (1<<2) /* report if tx fails */ #define TXCTL_802_3 (0<<3) /* 802.3 packet */ #define TXCTL_802_11 (1<<3) /* 802.
PayloadLen = len - 12; bap0_write(&PayloadLen, sizeof(PayloadLen)); bap0_write(pPacket, len); // issue the transmit command Cmd.Command = CMD_TRANSMIT; Cmd.Param0 = TxFid; if (issuecommand(&cmd, &rsp) != SUCCESS) return ERROR; if ( (rsp.
To allow for protocol encapsulation changes for transmission, a transmit FID gap of six bytes must be provided. (For FIDs with 802.3 Headers, recall that the 802.3 Header source address was reused for this purpose). The 6 byte gap is used even for management packets and for non-ethernet payloads. When using 802.11 headers, the host should read/write through the gap. The host must not use the offset to jump to the payload location.
Receiving an 802.11 Packet The following is sample code for receiving a packet, assuming that the 802.3 header reception has been disabled: typedef struct { /* receive control header */ unsigned long RxTime; /* time at start of 802.
if (rxpkt.CtlHeader.PayloadLen) { bap0_read(&rxpkt.payload, rxpkt.CtlHeader.PayloadLen); } // acknowledge reception OUT4500(EVACK, EV_RX); return SUCCESS; } Transmitting an 802.11 Packet When transmitting an 802.
The following is sample code for transmitting an 802.
TxCtlHDr.MaxShortRetry = numer of retries desired; if (bap0_setup(TxFid, 0x0000) != SUCCESS) return ERROR; bap0_write(&TxCtlHDr, sizeof(TxCtlHDr)); // write the 802.11 header bap0_write(p802Hdr, sizeof(*p802Hdr)); // write the gap bap0_write(&gapForTx802_11, sizeof(gapForTx802_11)); // write the payload if (lenPayload != 0) bap0_write(pPayload, lenPayload); // issue the transmit command Cmd.Command = CMD_TRANSMIT; Cmd.Param0 = TxFid; if (issuecommand(&cmd, &rsp) != SUCCESS) return ERROR; if ( (rsp.
FID Field Details Note, all fields are stored least significant byte first. Offset Name Receive Control Header +0x0000 RxTime Type Description u32 +0x0004 Status u16 +0x0006 PayloadLen u16 Receive time (beginning of packet) in usec relative to the TSF of the current cell. The status field for receive FIDs will return as zero. 0x0002 – CRC32 error (RF Monitor Mode Only) The length of the payload. (Does not include the Mac Header or 802.3 Header).
+0x000A +0x000C AID TxRetry u16 u16 +0x000E TxAssociationCou nt u8 +0x000F Transmit Bit Rate u8 +0x0010 +0x0011 +0x0012 MaxLongRetries MaxShortRetries Reserved u8 u8 u8[2] 802.11 Header +0x0014 +0x0016 FrameControl Duration u16 u16 +0x0018 +0x001E +0x0024 +0x002A Addr1 Addr2 Addr3 Sequence u8[6] u8[6] u8[6] u16 +0x002C Addr4 u8[6] +0x0032 GapLen u16 Aironet Wireless Communications, Inc.
+0x0034 Gap[ ] u8[Ga pLen] 802.3 Header +0x0034** Status u16 +0x0036** PayloadLen u16 +0x0038** +0x003E** DstAddr SrcAddr u8[6] u8[6] +0x0044** Payload u8[Pa yload Len] The gap field allows for changes in protocol encapsulation by the firmware. For transmit, the following section must be filled in if the TxControl.Type is 802.3. This is a duplicate of the status field from the control header. This is a duplicate of the payload length from the control header. Destination address.
Resource Identifiers Resource Identifiers (RIDs) are used to access configuration, status and statistics from the PC4500/4800. Selector Access Description Notes Configuration (these RIDs cannot be written while the MAC is enabled) 0xFF10 0xFF11 0xFF12 0xFF13 0xFF14 See notes See notes See notes See notes See notes Many configuration items. List of SSIDs which the station may associate to. List of APs which the station may associate to.
General Configuration Parameters The following describes the general configuration block.
+0x001A LongRetryLimit u16 0 default 16 +0x001C TxMSDULifetime 0 default 5000 +0x001E RxMSDULifetime 0 default 10000 0 will select the factory default [~10 sec] +0x0020 Stationary u16 (kus) u16 (kus) u16 Long Retry Limit (see 802.11). 0 selects factory default. 0 will select the factory default [~5 sec]. 0 0 +0x0022 +0x0024 Ordering Device Type u16 u16 0 0 0 0 +0x0026 Reserved u8[10] 0’s 0 If set, indicates that the radio is stationary.
+0x004A MaxBeaconLostTime u16 (kus) 0 default 500 +0x004C RefreshInterval u16 (kus) 0 default -1 disables 10000 If no beacons are received for this time period, the unit will begin rescanning. 0 selects factory default. Internally this will be converted to the number of consecutively missed beacons that may occur before rescanning. A minimum of eight consecutive missed beacons starts rescanning. At the specified interval, the station will send a refresh (null packet) to the AP.
+0x0072 Diversity u16 0 default 0x0303 +0x0074 TransmitPower u16 (mw) 0 default 250 or 100 +0x0076 +0x0078 Modulation Type u16 u16 0 default 0 default 0 1 +0x007A Reserved u8[8] 0’s 0’s This field is bit-mapped to select the operational antennas. The lower byte selects active receive antennas. The upper byte selects active transmit antennas.
the PC4500/4800 is not currently associated to an access point. The packet will be transmitted when the PC4500/4800 does finally associate, or will be removed from the queue when the transmit lifetime expires for the packet whichever occurs first. Station IBSS Operation In IBSS mode, also referred to as adhoc mode, the PC4500/4800 will scan for an appropriate wireless network and then join that network by synchronizing to the hopping pattern (if enabled).
Payload types The PC4500/4800 may be configured to transmit and receive packet payloads as is (LLC host) or as ethernet payloads. Ethernet payloads have an ethertype field as the first word of the payload. These payloads must be modified for transmission on the 802.11 network. Details of this are discussed under encapsulation. The receive payload type is selected with the PayloadType bit of the OperatingMode field of the General Configuration.
Station Mac Address Used to override the factory assigned address. Power Save Operation Power save operation is only supported in station mode. Access points are not allowed to operate in power save mode. Power Save Support by the Host For maximum power savings some cooperation is required from the host. Maximum savings can be achieved if the PC4500/4800 is aware that the host will not access the PC4500/4800.
WEP Key Non-volatile Reading rid 0xFF16 returns the next key. Reading rid 0xFF16 does not return the key. It returns the u16KeyLen. Non-zero values in these fields can be used to determine if a key has been set. Writing this rid sets the key in non-volatile storage. The only valid length for u16KeyLen is 5 or 0. The address {1, 0, 0, 0, 0, 0} is used to denote the default key. This is also the only valid address. U16KeyIndex is always 0.
Valid AP List The AP list contains up to four specified APs that may be matched. This allows a user to limit a unit to a subset of APs. Multicast addresses are not allowed. A zero address ends the list. Note, all addresses should be null (all zero’s) to disable the specified AP feature.
Encapsulation Transformations This section is only applicable to hosts that require ethernet style payloads. If the host has configured the card for LLC payloads, ie. unmodified payloads, (see OperatingMode in the General Configuration) then all payloads will pass through as is. 802.11 networks require 802.3 payload encapsulations. The PC4500/4800 will translate transmitted payloads and received payloads as required for ethernet hosts.
Capabilities RID This RID indicates the capabilities of the radio.
Status RID This RID indicates the current status of the radio.
Statistics RID Statistics are available as both 16-bit and 32-bit structures. All the statistics structures are read-only, however, the delta statistics may be cleared using the 0xFF62 or 0xFF6A RID. 16-bit Offset +0x0000 --+0x0002 32-bit Offset +0x0000 +0x0002 +0x0004 +0x0004 +0x0006 +0x0008 +0x000C +0x0008 +0x0010 +0x000A +0x000C +0x000E +0x0014 +0x0018 +0x001C Tal.RxPlcpCrcErr Tal.RxPlcpFormat Err Tal.RxPlcpLength Err Tal.RxMacCrcErr Tal.RxMacCrcOk Tal.RxWepErr +0x0010 +0x0020 Tal.
+0x0040 +0x0042 +0x0044 +0x0080 +0x0084 +0x0088 +0x0046 +0x008C +0x0048 +0x0090 +0x004A +0x0094 +0x004C +0x0098 +0x004E +0x009C +0x0050 +0x0052 +0x0054 +0x0056 +0x0058 +0x005A +0x005C +0x005E +0x00A0 +0x00A4 +0x00A8 +0x00AC +0x00B0 +0x00B4 +0x00B8 +0x00BC +0x0060 +0x0062 +0x0064 +0x0066 +0x0068 +0x006A +0x006C +0x006E +0x00C0 +0x00C4 +0x00C8 +0x00CC +0x00D0 +0x00D4 +0x00D8 +0x00DC +0x0070 +0x00E0 +0x0072 +0x0074 +0x0076 +0x00E4 +0x00E8 +0x00EC +0x0078 +0x007A +0x007C +0x007E +0x0080 +0x
+0x008A +0x0114 +0x008C +0x0118 +0x008E +0x011C +0x0090 +0x0120 +0x0092 +0x0124 +0x0094 +0x0128 +0x0096 +0x012C +0x0098 +0x0130 +0x009A +0x0134 +0x009C +0x0138 +0x009E +0x013C +0x00A0 +0x0140 +0x00A2 +0x0144 +0x00A4 +0x0148 +0x00A6 +0x014C +0x00A8 +0x00AA +0x00AC +0x00AE +0x00B0 +0x00B2 +0x00B4 +0x0150 +0x0154 +0x0158 +0x015C +0x0160 +0x0164 +0x0168 +0x00B6 +0x016C +0x00B8 +0x00BA +0x00BC +0x00BE +0x00C0 +0x0170 +0x0174 +0x0178 +0x017C +0x0180 Tal.ReasonStatus 5 Tal.
Some counts can be derived: TOTAL_RX_ERRORS = Tal.RxOverrunErr + Tal.RxPlcpFormatErr + Tal.RxPlcpLengthErr + Tal.RxMacCrcErr TOTAL_RX_OK = Tal.RxMacCrcOk TOTAL_RX_ATTEMPTS = TOTAL_RX_ERRORS + TOTAL_RX_OK MISC_RADIO_RX_DISCARDS = Tal.SsidMismatch + Tal.ApMismatch + Tal.RatesMismatch + Tal.RxFragDisc TOTAL_RETRIES = Tal.RetryLong + Tal.RetryShort PROTOCOL_OVERHEAD_RX_FRAMES = Tal.RxMan + Tal.RxRefresh + Tal.Rx.Poll + Tal.RxBeacon + Tal.RxAck + Tal.RxCts + Tal.
Power Save Operation Several levels of power save are implemented in the PC4500/4800: PSP Fast-PSP Should be used in the cases where small amounts of data are intermittently transferred (example = a handheld scanner used to read bar codes and use the information to query a database) Can be used in the cases where large amounts of data are intermittently transferred. Will result in a more efficient use of battery as well as effecting a quicker data transfer.
packet, or to transmit a packet, the host must first awaken the PC4500/4800 by setting EvAck.Awaken. This must be done twice without any delays: void awaken_4500(void) { push_interrupt_enable_state(); disable_interrupts(); OUT4500(EVACK, EV_AWAKEN); OUT4500(EVACK, EV_AWAKEN); pop_interrupt_enable_state(); } // first awakens // second does actual write After some delay, which could be 50 milliseconds or more, the PC4500/4800 will issue an EvStat.Awake event. The host should then acknowledge this (EvAck.
NOTE: THE FOLLOWING PSUEDO CODE ONLY APPLIES TO INFRASTRUCTURE MODE. Psp.CurListenInterval = FastListenInterval Psp.CurDecayValue = ListenDecay while (1) { wait until allowed to sleep; // allowed to go back to sleep as soon as there is no traffic pending to us (no directed or multicast) // and we have nothing to transmit -- there is no minimum time that we must stay awake for while (not allowed to sleep) { if (receive directed packet) Psp.CurListenInterval = 0; if (transmit packet) Psp.
8 CHAPTER 8 A PLAP Serial Client Software Interface This chapter details the Peripheral Link Access Protocol (PLAP) software interface to the PC4500/4800 when using serial mode. Introduction PLAP is a half-duplex formalized handshaking method of transferring data. The PC4500/4800 processor connects like a peripheral device to a host PC’s asynchronous serial port. The serial connection must operate at a single standard baud rate in the range of 7200bit/s to 115.2kbit/s.
can be made reliable by design since the cable lengths are short. The normal transport layer protocols used in network operating systems are therefore sufficient for reliable transport of application frames. A host application (or driver) may choose to occasionally send a SYNC_REQ frame to verify cable connectivity still exists by the receipt of a SYNC_ACK frame.
Frame Type Length Parameter #1 Parameter #2 • • • Data Checksum Closing byte Figure 8.1 - PLAP Packet Format The PLAP frame consists of the following fields. • • • • • The first field is Frame Type which identifies the type of frame. Several types are defined and described in the next sections. The Most Significant Bit (MSB) is used to indicate if the checksum field is operational (see checksum field description below).
Migrating from the LM2000 to the PC4500/4800 The PC4500/4800 supports the same PLAP frame format as the LM2000. The SYNC_REQ, SYNC_ACK, DATA and DOWNLOAD frames are identical between the two products. In order to take full advantage of the PC4500/4800, the user must support the new HOST_COMMAND and COMMAND_RESPONSE frame types. A minimal requirement for migration is the implementation of the use of two stop bits.
SYNC_ACK Frame Type: 0x01, 0x81 struct sync_ack_frm { unsigned char Frame_type; unsigned short Length; unsigned short Checksum; unsigned char EOT; }; // 0x01 , 0x81 // 0x0006 // 0x0007, 0x0087 // 0x04 The SYNC_ACK frame is sent in response to a SYNC_REQ frame. This frame is always sent before any other frame that may be pending.
CONFIGURE Frame Type: 0x04, 0x84 Configure type 0x10: // Default Values struct config16_frm { unsigned char unsigned short unsigned char unsigned short unsigned char unsigned char unsigned char unsigned char unsigned short unsigned short unsigned short unsigned char unsigned short unsigned char }; Frame_type; Length; Type; SSIDlen; SSID[32]; SupportedRates[8]; StationMacId[6]; NodeName[16]; PowerSaveMode; ScanMode; DsChannel Reserved[14]; Checksum; EOT; // 0x04, 0x84 // 0x005B // 0x10 // 0x0007 // ‘tsunam
Download type 0x01: // Default Values struct mode_request_frm { unsigned char Frame_type; unsigned short Length; unsigned char Type; unsigned short Checksum; unsigned char EOT; }; // 0x07, 0x87 // 0x0007 // 0x01 // 0x000F, 0x008F // 0x04 Download type 0x81: // Default Values struct mode_response_frm { unsigned char Frame_type; unsigned short Length; unsigned char Type; unsigned char Current_mode; unsigned char unsigned short unsigned char }; // 0x07, 0x87 // 0x0009 // 0x81 // 0x01=normal; 0x02=upgrade mo
Download type 0x83: // Default Values struct params_response_frm { unsigned char Frame_type; unsigned short Length; unsigned char Type; unsigned char Boot_vmjr; unsigned char Boot_vmnr; unsigned char Oper_vmjr; unsigned char Oper_vmnr; unsigned char Man_code; unsigned char Dev_code; unsigned char Dload_ksize; unsigned char Opfrm_kaddr; unsigned short Checksum; unsigned char EOT; }; // 0x07, 0x87 // 0x000F // 0x83 // 0x01 // 0x00 // xxxx // 0x04 Download type 0x04: // Default Values struct erase_resquest_
Download type 0x05: // Default Values struct prog_request_frm { unsigned char Frame_type; unsigned short Length; unsigned char Type; unsigned char Prog_ksize; unsigned short Prog_kaddr; unsigned short Prog_chksum; unsigned char Data[1024]; unsigned short Checksum; unsigned char EOT; }; // 0x07, 0x87 // 0x040C // 0x05 // 0x01 // packet no.
The proper sequence used to perform a firmware upgrade is to: 1. Send the mode request. 2. Receive the mode response. 3. Send the parameter request. 4. Receive the parameter response. 5. Issue the set mode command (mode = 2 for firmware download). 6. Issue the erase flash command. 7. Receive the erase confirm response. 8. Issue sequential program block frames until complete binary file is transferred. 9. Alternately receive program block responses. 10. Issue the firmware enable command. 11.
When using Type=0x00, the “Command” parameter must be one of the following values. 0x0010 NOP 0x0001 Enable 0x0002 Disable 0x0003 Lose Sync 0x0004 Soft Reset 0x0008 Read Configuration 0x0021 Read RID 0x0108 Write Configuration 0x0121 Write RID (RID structure is used to pass the info) Refer to chapter 7 for RID structures. 0x003E Set PHY registers 0x003F Transmitter testing (RID structure is used to pass the info) Refer to Transmitter testing below.
COMMAND_RESPONSE Frame Type: 0x11, 0x91 // Default Values struct command_response_frm { unsigned char Frame_type; unsigned short Length; unsigned char Type; unsigned short Status; unsigned short Response0; unsigned short Response1; unsigned short Response2; // 0x11, 0x91 // xxxx // 0x?? struct { RID // Optional // returned on a Read RID // command only Checksum; EOT; // xxxx // 0x04 }; Unsigned short Unsigned char }; The COMMAND_RESPONSE frame is sent in response to a HOST_COMMAND frame.
PLAP Boot Strap of PC4500/4800 The following is the correct start sequence for PLAP mode. 1. Wait for Card Detect signals to go active (active LOW). *** 2. Enable power (VCC) to the socket. Set VPP1 = 5V, VPP2 = 0V. 3. Delay for power to stabilize (200 ms). 4. Assert PCMCIA reset. 5. Release PCMCIA reset. 6. Delay at least 10us. 7. Wait for Card Ready to go active. Alternately, delay 3 seconds. 8. Send autobaud sequence at selected baud rate (0x0D,0x0D,0x0D,0x33).
Aironet Wireless Communications, Inc.
Aironet Wireless Communications, Inc.
P A R T 5
9 CHAPTER 9 A OEM Radio Approval Information This chapter contains information about the approvals, regulations, labeling requirements and configuration of the PC4500/4800 radio modules for operation in various countries. Approvals Safety The PC4500/4800 is designed to meet the requirements of UL, CSA, VCCI and is compliant to the European Low Voltage Directives. However, the OEM is responsible for the individual safety agency approval of the entire OEM product.
compliance to CFR 47 Parts 2 and 15. Aironet’s FCC approval covers the radio and approved antennas only. The use of antennas not approved by the FCC for use with the Aironet radio is in violation of the FCC rules. Using FCC approved antennas If the OEM is using an Aironet FCC approved antenna, the OEM will be required to test the entire OEM product to Part 15 Subpart B for unintentional radiators. No additional FCC application or paperwork will be required concerning the radio itself.
responsibility to contact the European local authorities, Competent Body or Notified Body test lab to determine what applicable standards need to be applied for the product. The OEM can obtain the appropriate approval numbers and copy of certifications of the radio from their Aironet Sales agent. The OEM will be required to test the OEM product with the radio installed to the requirements of EN 55022, EN 50082-1 and the Low Voltage Directive. The PC4500/4800 is designed to meet EN 55022 Class B levels.
OEM Labeling Requirements US and US Territories In accordance with FCC rules, the OEM product must have the radio approval number on the product label. This can be a second label added to the outside of the product.
AWCSETEE Operation A DOS-based utility called AWCSETEE is available for setting the EEPROM in the PC4500/4800 to specify the country of operation. Different countries have different sets of frequencies that are allowed in the 2.4GHz band. In order to operate on the correct frequencies, the country code must be set in the EEPROM that will tell the firmware which frequencies to operate on. When the PC4500/4800 is ordered, it is programmed to operate in the country to which it will be shipping.
Appendix A – PC4500/4800 Troubleshooting The PC4500/4800 provides LED messages and error codes. This chapter provides the general procedures for correcting common problems encountered when installing the PC4500/4800 system. Indicator LEDs The PC4500/4800 has two indicator LEDs located on the face of the card: one green and one amber. The Green LED is the Link Integrity/Power LED. It glows when the card is receiving power and flashes when the PC4500/4800 is linked with the network.
Power Requirements Table A.4 - Power Requirements Specification Value Operational Voltage 5.0 ±0.25 Volts Receive Mode Current 280 mA Low Power Transmit Mode Current 400 mA at 50 mW High Power Transmit Mode Current 490 mA at 100 mW Standby Mode Current 5 mA Aironet Wireless Communications, Inc.
Appendix B – PC4500/4800 PCMCIA CIS Description (Subject to change without notice) Offset (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10-1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31,32 33,34 35 Table B.
36 37 38 39 3A 3B 02 03 07 1A 05 01 3C 3D,3E 05 E0,03 3F 07 40 41 42 1B 0C C5 43 44 45 46 47 48 49 4A 4B-4D 4E,4F 01 1A 09 55 66 01 55 46 30,FF,FF FF,FF Link to 0x39 LAN Media 2.
Appendix C - Reflashing the Firmware on the PC4500/4800 To reflash the firmware on the PC4500/4800 adapter, use the FLASH.EXE utility. It will correctly interact with the card to accomplish the reflash. However, if you wish to reflash the card without using the FLASH.EXE utility, the following procedure must be used: 1. Apply VCC=5V, VPP1=5V, VPP2=5V. 2. Delay 200ms. 3. Enable output pins and assert RESET. 4. Deassert RESET. 5. Wait for card ready. 6.
Communicating with the Loader Program Transmit: To transmit a byte to the card, use RAM address 0x0028 which translates to the MAC processor SW_SUPPORT0 register. To transmit a byte, first wait until D15 of the word at 0x0028 is clear. Then write the desired byte to 0x0028 with D15 set to logic ‘1’. D15 is the busy bit - If D15 is set, the transmit register is full. If D15 is clear, you may write to the transmit register without overwriting anything.
Aironet Wireless Communications, Inc.
