Technical data

Troubleshooting 5
U4154A Logic Analyzer Service Guide 71
• That individual locations can be independently addressed.
• The EEPROM can be block erased.
Probe ID Read Test
The purpose of this test is to verify that the Probe ID values
can be correctly read and to verify the functionality of the
Digital to Analog Converter by testing the two Probe ID DAC
outputs at various voltage levels.
Chip Registers Read/Write Test
The purpose of this test is to verify that each bit in each
register of the Analysis chip can be written with a 1 and 0
and read back again. The test also verifies that a chip reset
sets all registers to their reset condition (all 0s for most
registers).
Freq Synth Lock Detect Test
This test determines if all the voltage- controlled oscillators
(VCOs) are working properly.
Acquisition Chip BIST Test
Tests the Timing Zoom memory and other internal memories
on the acquisition chip.
Resource Bus Connection Test
This test is only run if there are two or more U4154A logic
analyzer cards in adjacent slots in a chassis.
This test verifies whether or not the flex cables are squarely
and firmly inserted into the connectors.
Comparator Programming Test
The purpose of this test is to verify the programming path
to each of the comparators.
Comparator/DAC Test
This test is executed only if all probes are detached.