Technical data

SCPI Status Registers 2
U2751A Programmer’s Reference Guide 11
Status Byte Register
The Status Byte summary register reports conditions from the other status
registers. The bits are not cleared when you read the register.
Bit Definitions: Status Byte Register
The Status Byte summary register will be cleared when:
• you execute the clear status (*CLS) command
• querying the Standard Event register (*ESR? command will clear only
bit 5 in the summary register)
The Status Byte Enable register is cleared when you execute the *SRE 0
command.
Bit number Decimal value Definition
0 Not Used 1 Always zero.
1 Not Used 2 Always zero.
2 Error Queue 4 There is at least one error code in the error queue. Use the
SYSTem:ERRor? command to read and clear the error from the
queue.
3 Not Used 8 Always zero.
4 Message Available 16 Data is available in the instrument's output buffer.
5 Standard Event 32 One or more bits are set in the Standard Event register (bits must be
enabled, refer to the *ESE command).
6 Master Summary 64 One or more bits are set in the Status Byte register and may
generate a Request for Service (RQS). Bits must be enabled using
the *SRE command.
7 Not Used 128 Always zero.