Programming instructions

Programming the Status Register System
Status Groups
Chapter 3128
Data Questionable Frequency Condition Register
The Data Questionable Frequency Condition Register continuously monitors the hardware
and firmware status of the signal generator. Condition registers are read-only.
Data Questionable Frequency Transition Filters (negative and positive)
Specifies which types of bit state changes in the condition register set corresponding bits in
the event register. Changes can be positive (0 to 1) or negative (1 to 0).
Table 3-8 Data Questionable Frequency Condition Register Bits
Bit Description
0 Synthesizer Unlocked. A 1 in this bit indicates that the synthesizer is unlocked.
1 10 MHz Reference Unlocked. A 1 in this bit indicates that the 10 MHz reference signal is
unlocked.
2 1 GHz Reference Unlocked. A 1 in this bit indicates that the 1 GHz reference signal is
unlocked.
3, 4 Unused. These bits are always set to 0.
5 Sampler Loop Unlocked. A 1 in this bit indicates that the sampler loop is unlocked.
6 YO Loop Unlocked. A 1 in this bit indicates that the YO loop is unlocked.
7−14 Unused. These bits are always set to 0.
15 Always 0.
Query: STATus:QUEStionable:FREQuency:CONDition?
Response: The decimal sum of the bits set to 1
Commands:
STATus:QUEStionable:FREQuency:NTRansition <value> (negative) or
STATus:QUEStionable:FREQuency:PTRansition <value> (positive) where
<value> is the sum of the decimal values of the bits you want to enable.
Queries:
STATus:QUEStionable:FREQuency:NTRansition?
STATus:QUEStionable:FREQuency:PTRansition?