Programming instructions

Programming the Status Register System
Status Groups
Chapter 3 121
Data Questionable Condition Register
The Data Questionable Condition Register continuously monitors the hardware and firmware
status of the signal generator. Condition registers are read only.
Table 3-6 Data Questionable Condition Register Bits
Bit Description
0, 1, 2 Unused. These bits are always set to 0.
3 Power (summary). This is a summary bit taken from the QUEStionable:POWer
register. A 1 in this bit position indicates that one of the following may have happened:
The ALC (Automatic Leveling Control) is unable to maintain a leveled RF output power
(i.e., ALC is UNLEVELED), or the reverse power protection circuit has been tripped.
4 Temperature (OVEN COLD). A 1 in this bit position indicates that the internal
reference oscillator (reference oven) is cold.
5
Frequency (summary). This is a summary bit taken from the
QUEStionable:FREQuency register. A 1 in this bit position indicates that one of the
following may have happened: synthesizer PLL unlocked, 10 MHz reference VCO PLL
unlocked, heterodyned VCO PLL unlocked, sampler, or YO loop unlocked. For more
information, see the “Data Questionable Frequency Status Group” on page 127.
6 Unused. This bit is always set to 0.
7 Modulation (summary). This is a summary bit taken from the
QUEStionable:MODulation register. A 1 in this bit position indicates that one of the
following may have happened: modulation source 1 underrange, modulation source 1
overrange, modulation source 2 underrange, modulation source 2 overrange, or
modulation uncalibrated. See the Data Questionable Modulation Status Group for more
information.
8 Calibration (summary). This is a summary bit taken from the
QUEStionable:CALibration register. A 1 in this bit position indicates that one of the
following may have happened: an error has occurred in the DCFM/DCΦM zero
calibration or an error has occurred in the I/Q calibration. See the Data Questionable
Calibration Status Group for more information.
9 Self Test. A 1 in this bit position indicates that a self-test has failed during power-up.
This bit can only be cleared by cycling the signal generator’s line power. *CLS will not
clear this bit.
10, 11,
12, 13, 14
Unused. These bits are always set to 0.
15 Always 0.