User manual

56 Status Reporting

Table 4-5. Generating RQS from the CC Event

Operation PTR

STAT:OPER:PTR 1024

Allows a positive transition at the CC input (bit 10) to be

latched into the Status Event register.

Operation Enable

STAT:OPER:ENAB 1024

Allows the latched CC event to be summed into the OPER

summary bit.

Service Request Enable

*SRE 128

Enables the OPER summary bit from the Status Byte register to

generate RQS.

Operation Condition

STAT:OPER:EVEN?

When you service the request, read the event register to

determine that bit 10 (CC) is set and to clear the register for the

next event.

All bits of the PTR registers bits are set to 1 at power on or in response to STAT:PRES.

Adding More Operation Events

To add the CV (constant voltage) event to this example, it is only necessary to add the decimal values for bit 8 (value 64) to

the programming commands of the Operation Status group. The commands to do this are:

STAT:OPER:PTR 1280;ENAB 1280

It is not necessary to change any other registers, since the programming for the operation summary bit (OPER) path has

already been done.

Servicing Questionable Status Events

To add OC (overcurrent) and OT (overtemperature) events to this example, program Questionable Status group bits 1 and 4.

STAT:QUES:PTR 18;ENAB 18

Next, you must program the Service Request Enable register to recognize both the questionable (QUES) and the operational

(OPER) summary bits.

*SRE 136

Now when there is a service request, read back both the operational and the questionable event registers.

STAT:OPER:EVEN?;QUES:EVEN?

Monitoring Both Phases of a Status Transition

You can monitor a status signal for both its positive and negative transitions. For example, to generate RQS when the

power supply either enters the CC (constant current) condition or leaves that condition, program the Operational Status

PTR/NTR filter as follows:

STAT:OPER:PTR 1024;NTR 1024

STAT:OPER:ENAB 1024;*SRE 128

The PTR filter will cause the OPER summary bit to set RQS when CC occurs. When the controller subsequently reads the

event register (STAT: OPER: EVEN?), the register is cleared. When CC subsequently goes false, the NTR filter causes the

OPER summary bit to again set RQS.