Specifications

8
安捷倫科技高頻元件量測研討會
2/23/2006
Page 15
Analysis Case II :
ÆImpedance Control Verify by TDR/TDR System
Design Condition:
Substrate Type : 2 Layer
Impedance Control : Differential
Simulation Structure : Micro-Strip Line
Trace Width (W): 0.39mm
Trace Thickness (T): 22 um
Dielectric Thickness (T1): 200um
Separation (s): 0.15mm
Dielectric Layer
ε= 4.0
Signal Trace in 1st Layer
GND Plane in 2nd Layer
W
T
T1
S
TDR Measurement
Result
安捷倫科技高頻元件量測研討會
2/23/2006
Page 16
Trace width(um) separation(um) Zodd(ohm) Zeven(ohm) Single ended(ohm)
Q2D 388.95(from drawing) 150(from drawing)
41.2 58.8 50.9
Q2D 429um 116um
38.1267 55.6689 47.5768/435um
TDR 429um 116um 42.4~42.8
61.7
52.3~53
Im
p
edance com
p
arison
Impedance Control
-- Manufacture Result and comparison
SEM-single ended trace
width measurement
SEM-differential trace
width/space measurement
Design / Measurement Comparison