Technical data

Status Registers 3
Programmer’s Guide 25
Status Register System
The hardware status registers are combined to form the instrument
status system. Specific status bits are assigned to monitor various
aspects of the instrument operation and status. See the following
diagram of the status system for information about the bit assignments
and status register interconnections.
Figure 1 Agilent N9342C/43C/44C Status Register System
Setting and Querying the Status Register
Each bit in a register is represented by a numerical value based on its
location. This number is sent with the command to enable a particular
bit. To enable more than one bit, send the sum of all of the bits involved.
For example, to enable bit 0 and bit 6 of the standard event status
register, you would send the command *ESE 65 (1 + 64).
The results of a query are evaluated in a similar way. If the *STB?
command returns a decimal value of 140, (140 = 128 + 8 + 4) then bit 7
is true, bit 3 is true, and bit 2 is true.
Event Enable Reg
.
7
6
5
4
3
2
1
0
&
&
&
&
&
&
&
+
0
1
2
3
4
5
6
7
Status Byte Register (*STB?)
Unused
Unused
Error/Event Queue Summary
Unused
Message Available (MAV)
Std. Event Status Sum
Unused
Reserved
+
0
1
2
3
4
5
6
7
Standard Event Status Register
Unused
Unused
Query Error
Dev. Dep. Error
Unused
Command Error
Reserved
Power On
Service Request Enable Register
(*ESE,*ESE?,*ESR?,*)
(*SRE,*SRE?)